Investigation of CMOS Single Process Steps on 4H-SiC a-Plane Wafers for Quantum Applications

The crystal orientation of 4H-SiC a-plane (11-20) wafers allows efficient optical readout of silicon vacancies across the surface of the wafer. This sparks significant interest in utilizing a-plane wafers for quantum applications. Given the distinct properties of a-plane wafers compared to conventional c-plane (0001) wafers, well-established CMOS process steps require re-evaluation to ensure a fully functional CMOS process and comparable electrical properties. In epitaxial growth, the layer-by-layer growth on a-plane substrates leads to a smooth surface with a roughness of 0.08 nm. The incorporation of dopants is sevenfold increased, compared to c-plane substrates. For ion implantation on a-plane wafers, the 30° periodicity of (11-20) and (1-100) directions induces extended channeling, creating a 2D ion implantation profile with flanks in the ± 30° directions from the intended doping profile. For thermal oxidation a sixfold increased linear rate constant on a-plane wafers led to increased oxide growth rate in the reaction-limited regime.