Internal behavior of BCD ESD protection devices under very-fast TLP stress

BCD electrostatic discharge (ESD) protection npn devices with and without a sinker are analyzed experimentally and by device simulation. The device internal thermal and free carrier density distributions during vf-TLP and TLP stresses are studied by a backside transient interferometric mapping technique. Experimentally observed activity of lateral and vertical parts of the npn transistor are well reproduced by the simulation.