Development of a patterning process for releasing and sealing of post-CMOS MEMS pressure sensor membranes

In this work a sub-step of the fabrication of an absolute capacitive pressure sensor MEMS on top of a CMOS substrate is discussed. Especially for low pressure applications membrane diameters of more than 100 mm are required. A vapour phase etching of a sacrificial layer by side openings is assumed to be inappropriate due to the addressed diameters. To apply an isotropic HF-vapour phase etching process successfully, openings in the structural layer of the MEMS-structure to get access to the sacrificial layer have been utilized. Different designs of possible etch accesses are simulated regarding their impact on stress. It is shown that a diameter minimisation of vertical etch access tunnels is beneficial with respect to stress (under applied pressure) and regarding the conditions for sealing the cavity. Therefore, a side wall spacer process to minimise the diameters of vertical etch access tunnels to release MEMS-structures was developed. By the use of two applied hard masks the diameter of lithographically structured tunnels is reduced by about 260 nm.