Reduction of layout variations with stress-compensated hybrid STI fills: A comprehensive analysis

Based on a detailed I-V analysis, 2D/3D process/device simulation, and inline wafer bow measurements, we have investigated a number of stress-induced layout effects on MOSFET performance caused by hybrid STI fills (HARP/HDP and SOG/HDP). Variations of active area dimensions, STI widths, and gate lengths were studied in 58 nm DRAM technology. Excellent STI-stress-related device performance variability (overall current and Vth variations smaller than 5% / 10 mV) is demonstrated with a proper choice of STI full materials and adjusted layer thicknesses.