Development of an Adaptive Re-Distribution Patterning Process for Fan-Out Packages with Embedded High I/O Components

A solution to manufacture high-performance electronic systems with computing intensive functions in volume constrained products, is the utilization of miniaturized microsystems equipped with state-of-the-art embedded components densely integrated in build-up substrates via advanced patterning processes. Besides the requirements like a sufficient yield of the lithographic process itself in order not to lose the valuable high-density components, a major point of an RDL-last approach is to register each layer of the production panel to the corresponding device during RDL fabrication. One solution is, to measure the deviation of the target position towards the actual position, then digitally reroute the connections and finally feed forward the data into the process tools like a direct imaging system (DI). This paper publishes results from the EU funded project CHARM where AT&S has supplied embedded components 25 mm x 17 mm x 110 μm into panels to FHG IZM which are further connected to upper RDL build-up layers, resulting into fan-out panel level packages (FOPLP) with enlarged pitches compared to pitches on the components. All process steps toward FOPLP packaging will be elucidated and solutions to all encountered challenges will be shown and discussed. At the end, the computing modules stacked with advanced power modules have been the heart of the ADPU units in automotive electronics for autonomous mining vehicles demanded by CHARM end-users.