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  4. Three-valued automated reasoning on analog properties
 
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2007
Conference Paper
Title

Three-valued automated reasoning on analog properties

Abstract
We deal with the problem of designing suitable languages for the modeling and the automatic verification of properties over analog circuits. To this purpose, we suitably enrich classical temporal logics with basic formul\ae allowing to model arbitrary functions relating analog variables. We show how to automatically check the resulting CTLf formulæ on analog circuits. In particular, we rely on interval arithmetic methods and we extend to the analog context a number of techniques for the abstraction and the verification of digital systems, based on three-valued temporal logics.
Author(s)
Gentilini, R.
Schneider, K.
Dreyer, A.
Mainwork
ACM Great Lakes Symposium on VLSI 2007. Proceedings  
Conference
Great Lakes Symposium on VLSI (GLSVLSI) 2007  
DOI
10.1145/1228784.1228899
Language
English
Fraunhofer-Institut für Techno- und Wirtschaftsmathematik ITWM  
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