A synchronous FPGA design of a bilateral filter for image processing
In this paper a new FPGA design concept of a bilateral filter for image processing is presented. With the aid of this design the bilateral filter can be realized as a highly parallelized pipeline structure with very good utilization of dedicated resources. The innovation of the design concept lies in sorting the input data into groups in a manner that kernel based processing is possible. Another feature of the kernel based design concept is the increase of the clock to the quadruple of the pixel clock in the filter architecture. The sorting of the pixels and the quadruplication of the pixel clock are the key to the synchronous FPGA design using a parallelized pipeline architecture. The synchronicity of the design assures constant output delay which can be computed after the hardware specification is known. For acceleration of the design concept the separability and symmetry of the geometric filter component is utilized, also reducing the complexity of the design. Combined with parallel pipeline design a significant decrease of resource consumption can also be achieved. Thus the presented design can easily be implemented on a common medium sized FPGA.