A modified shifting bottleneck heuristic for scheduling wafer fabrication facilities

The Factory Operations portion of the 2001 International Technology Roadmap for Semiconductors (ITRS) indicates that real time scheduling is one of the potential solutions for the semiconductor industry to preserve the decades-long trend of 30% per year reduction in cost per function. However, scheduling wafer fabrication facilities is a very difficult problem. There are several main features that complicate scheduling these systems including: a large number of processing steps, re-entrant flows, batch tools, planned and unplanned equipment downtimes, sequence-dependent tool setups, high levels of automation, and the fact that some processing steps require auxiliary resources (e.g. reticles). The Semiconductor Research Corporation (SRC) and International SEMATECH recently created the Factory Operations Research Center (FORCe). As one of the initial set of FORCe projects, a team of researchers from two US and three German institutions were funded to investugate a shifting bottleneck heuristic-based approach to scheduling wafer fabrication facilities. In this paper, we briefly describe the FORCe program and discuss the four major research tasks associated with the three year scheduling project.