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  4. GePaRD - A High-Level generation flow for Partially Reconfigurable designs
 
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2008
Conference Paper
Title

GePaRD - A High-Level generation flow for Partially Reconfigurable designs

Abstract
This paper presents GePaRD, a novel approach to High-Level Synthesis of self-adaptive systems based on Partially Reconfigurable (PR) FPGAs. GePaRD combines Temporal Modularization and Temporal Placement in order to reduce the reconfiguration overhead at runtime by extracting Temporal Reusable Modules. We introduce the basics of High-Level PR design as well as the GePaRD design steps (transformations) and GePaRD descriptions (models). Moreover, we describe our approach to Temporal Modularization using Greedy Clique Partitioning and Temporal Placement using Simulated Annealing.
Author(s)
Boden, M.
Fiebig, T.
Reiband, M.
Reichel, P.
Rülke, S.
Mainwork
IEEE Computer Society Annual Symposium on VLSI, ISVLSI '08  
Conference
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2008  
DOI
10.1109/ISVLSI.2008.21
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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