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  4. Dry Etched through SiC Via (TSiCV) Process Analysis Using DOE Modeling
 
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December 2, 2020
Conference Paper
Title

Dry Etched through SiC Via (TSiCV) Process Analysis Using DOE Modeling

Abstract
This paper describes the research on modelling the etching parameters of SiC using RIE. The experiments were performed using a design of experiments (DOE) with a total 78 experiments and D-efficiency of over 85.4 finding the most significant process parameters impacting the etch result. All experiments were carried out for three different via diameters. The evaluation of the via etching was performed using confocal microscopy and by cross sections of the SiC vias. Afterwards the model was verified with etching experiments show very good match with the prediction model. The deviation between the model and the verification was below 6%.
Author(s)
Mackowiak, Piotr  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Schiffer, Michael  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Schneider-Ramelow, Martin  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Lang, Klaus-Dieter  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Mainwork
IEEE 22nd Electronics Packaging Technology Conference, EPTC 2020  
Conference
Electronics Packaging Technology Conference 2020  
DOI
10.1109/EPTC50525.2020.9315121
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
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