TEM investigation of time-dependent dielectric breakdown mechanisms in Cu/Low-k interconnects

The time-dependent dielectric breakdown (TDDB) in on-chip interconnect stacks is one of the most critical failure mechanisms for microelectronic devices. The aggressive scaling of feature sizes, both on devices and interconnects, poses serious challenges to ensure the required product reliability. Conventional reliability tests and post-mortem failure analysis provide only limited information about the physics of failure mechanisms and degradation kinetics. Therefore it is necessary to develop new experimental approaches and procedures to study the time-dependent failure mechanisms and degradation kinetics in particular. In this paper, comprehensive transmission electron microscopy (TEM), particularly an in-situ experimental methodology, is demonstrated to investigate the TDDB degradation and failure mechanisms in Cu/low-k interconnect stacks. A dedicated ""tip-to-tip"" test structure is designed in the 32 nm complementary metal-oxide-semiconductor (CMOS) technology node to restrict the failure site, and is the key basis for the in-situ and ex-situ TEM investigations. High quality imaging and chemical analysis are used to identify the failure mechanism and study the kinetic process. The in-situ electrical test is also integrated into the in-situ TEM investigation to provide an elevated electric field to the dielectrics. Electron tomography is utilized to characterize the directed Cu diffusion in the insulating dielectrics. These experimental approaches open a different possibility to study the TDDB failure mechanism in interconnect stacks of microelectronic products, and it could also be extended to other structures in active devices.