Simulation of mixed signal systems in standard VHDL
Historically the analogue and digitel parts of a hardware design have been modelled and simulated in different environments and could not be combined in a single simulator. On the other hand, if a design contains both analog and digital parts simulating their interactions are most important to reliably verify the design. Therefore, we present a method for simulating analogue circuits and digital components in a VHDL simulator. For executing analogue simulations in a VHDL environment an analogue simulator has been developed. It permits to model linear and non-linear circuits using only standard VHDL language elements. This fact allows a similar conversion of this method to different VHDL environments. A netlist is used to model the analogue parts with elements from a model library. In order to interface analogue and digital parts A/D and D/A converter elements are be used. This allows signal feedbacks between both parts during the simulation.