A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models

Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower abstraction levels, conservative assumptions are usually applied which often result in suboptimal performances such as area and power consumption. In order to enable both early performance estimates and fast iteration cycles, we combined the estimation of parasitics from template-based layout generators with SystemC-based parameterizable modelling. As a result, we can compute layout-aware performance estimates of a configurable capacitive pipeline ADC within a runtime of only about one minute per iteration. Using this estimation in a loop, we analyzed and optimized substantial parameters of a capacitor array in order to improve the ADC’s performance.