Performance and Power Analysis of LPDDR6

The LPDDR6 DRAM standard has been released recently by JEDEC. With the specification of the new low-power DRAM being published, previously disclosed details have been confirmed, and further information about the standard became available. Key improvements of LPDDR6 over the current LPDDR5X standard include a 69% increase in the data rate to up to 14,400 MT/s and a shift from 16-bit to 24-bit channels composed of two independent 12-bit sub-channels. The burst length increased from 16 to 24, resulting in a total burst size of 288 bits. Of these, 256 bits are allocated to user data and 32 bits are reserved for metadata intended for RAS or power-saving features. As an additional power optimization, LPDDR6 introduces a new efficiency mode that disables one of the sub-channel interfaces and allows access to the banks of both sub-channels through a shared interface. In this paper, we provide an in-depth analysis of the performance of LPDDR6 with various applications under real conditions and compare it to its predecessor LPDDR5. We also evaluate the impact of the newly introduced efficiency mode on both the performance and power consumption. Our findings provide system architects with an understanding of what to expect from an upgrade to LPDDR6, as well as guidance on when switching to the efficiency mode is beneficial.