Current challenges in interposer and 3D-design

While 3D integration technologies become more and more mature on the design side several issues still remain. This talk addresses the routing problem for interposers in conjunction with warping and cost. An interposer design according to the new JEDEC 229 wide I/O standard is presented. Furthermore the floorplanning tool for 3D-ICs developed at Fraunhofer IIS/EAS is presented and the work flow is discussed.