Design automation for systems on a chip realized in leading edge manufacturing technologies

The devices and interconnect structures of new semiconductor technologies for very complex systems on a chip show parasitic physical effects with growing influences of the circuit behavior. Therefore the design technology has to be further developed and tailored for requirements concerning high system performance and reliability. The influences of parasitic effects and parameter variations on the circuit behavior have to be minimized within the design process. Typical parasitic effects of two important technologies are discussed in this paper, the nano-scale CMOS technology and the Vertical System Integration. The influences of electro thermal coupling, electromagnetic coupling, leakage current, and parameter variations to the circuit behavior are identified and modeled. Approaches for minimization of these influences by designing are presented.