Introducing the universal verification methodology (UVM) in SystemC and SystemC-AMS

This presentation introduces the Universal Verification Methodology (UVM) built in SystemC/C++ (UVM-SystemC), to advance current system-level verification practices. UVM-SystemC enables the creation of structured, modular, configurable and reusable testbench environment. Unlike other initiatives to create UVM in SystemC, the presented proof-of-concept class library uses identical constructs as defined in the UVM standard for test and sequence creation, verification component and testbench configuration and execution by means of simulation. Users familiar with either SystemC and/or UVM will immediately feel comfortable to start using UVM-SystemC right away. In a nutshell, the talk describes the concepts of UVM-SystemC and shows how they can be applied to real-world designs from the digit al and mixed-signal domains: Basic UVM classes and their function are introduced Differences with respect to UVM in SystemVerilog are highlighted (Hierarchical) UVM sequences describing test scenarios are discussed Example: SystemC AMS timed dataflow driver in UVM-SystemC UVM-SystemC has been developed in the research project VERDI (Verification for heterogeneous Reliable Design and Integration, funded by the European Union's Seventh Framework Programme (FP7), including the partners NXP, Infineon, Continental, Magillem, UPMC, and the Fraunhofer Institute for Integrated Circuits. The UVM-SystemC Language Reference Manual and associated class library will be handed to the Accellera Systems Initiative enabling further development and standardization.