English
Deutsch
Log In
Log in with Fraunhofer Smartcard
Password Login
Research Outputs
Fundings & Projects
Researchers
Institutes
Statistics
Fraunhofer-Gesellschaft
Home
Fraunhofer-Gesellschaft
Konferenzschrift
3d Wafer Level Packaging By Using Cu-Through Silicon Vias For Thin Mems Accelerometer Packages
Details
Full
Export
Statistics
Options
Show all metadata (technical view)
2015
Conference Paper
Title
3d Wafer Level Packaging By Using Cu-Through Silicon Vias For Thin Mems Accelerometer Packages
Author(s)
Hofmann, Lutz
Reuter, Danny
Schubert, I.
Wünsch, Dirk
Rennau, Michael
Ecke, Ramona
Vogel, Klaus
Gottfried, Knut
Schulz, Stefan E.
Geßner, Thomas
Mainwork
12th Annual International Wafer-Level Packaging Conference, IWLPC 2015
Conference
International Wafer-Level Packaging Conference (IWLPC) 2015
Language
English
Fraunhofer-Institut für Elektronische Nanosysteme ENAS