A 2-0 MASH Delta-Sigma ADC with sub-sampling SAR ADC

In this paper, a 2-0 multi-stage noise-shaping (MASH) Delta-Sigma Analog-to-Digital converter (ADC) with a successive-approximation-register (SAR) ADC as second-stage is proposed. The SAR ADC is running with a reduced sample rate, which relaxes its requirements. The digital combination of the Delta-Sigma modulator (DSM) and the SAR ADC cancels the quantization error of the first stage despite the sub-sampling of the second path. The overall performance is improved. The signal-to-noise and distortion ratio (SINAD) increases after filtering with a digital noise cancelation filter similar to a second order cascaded-integrated-comb (CIC) filter from 36.7dB to 61.0dB for a bandwidth of 1MHz. The SINAD increases with the second filter stage implemented as a configurable infinite-impulse-response (IIR) filter (in this case a 6th-order IIR filter) with a bandwidth of 400kHz to 52.7dB for the DSM output and to 72.0dB for the DSM output combined with the SAR ADC. For sharper filtering the total resolution increases further. The architecture is suitable for high-bandwidth and low oversampling ratio (OSR) applications.