An Iterative Surface Potential Algorithm including Interface Traps for Compact Modeling of SiC-MOSFETs

Surface potential-based compact models are an essential link between circuit simulation and technology due to their physical base. Such models are particularly important for the development of devices and circuits based on new wide-bandgap semiconductors such as silicon carbide (SiC) where additional physical phenomena in comparison to silicon are considered. An efficient computation of the surface potential (F S ) is one of the core components of F S -based compact models. We developed a fast and robust iterative algorithm for the surface potential, which takes the specific interface trap distribution of SiC-MOSFETs into account. Therefore, a new initial guess is derived, which reduces the number of required iteration steps by 40% in contrast to the common initial guess for silicon devices. Furthermore, different starting equations and types of iteration steps are compared in terms of convergence speed and stability over a wide range of densities of interface traps, technology parameters, and operating conditions.