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Design process supporting simulations on wafer level packages
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2003
Conference Paper
Title
Design process supporting simulations on wafer level packages
Author(s)
Sommer, J.-P.
Wittler, O.
Manessis, D.
Michel, B.
Mainwork
DTIP of MEMS & MOEMS: Design, test, integration and packaging of MEMS/MOEMS 2003
Conference
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) 2003
DOI
10.1109/DTIP.2003.1287006
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM
