Internal behavior of BCD ESD protection devices under TLP and very-fast TLP stress

BCD electrostatic discharge (ESD) protection npn devices with different layout variations are analyzed experimentally an by device simulation. The device internal thermal and free carrier density distributions during the transmission line pulse (TLP) and very-fast transmission line pulse (vf-TLP) stresses are studied by a backside transient interferometric mapping technique. The lateral part of the npn transistor dominates the devices operation. The action of the vertical part of the transistor is influenced by the device layout. Experimentally observed activity of both parts of the npn transistor is well reproduced by the simulation. The devices exhibit an excellent ESD performance at both TLP and vf-TLP stress.