3D capacitive interconnections for high speed interchip communication

A 3D Interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13m CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15×15m2 a wide range of operating frequency up to 900M H z with an energy consumption of 41 f J/bit. In the asynchronous scheme we demonstrate with electrodes 8×8m2 a vertical propagation of clock at 1.7GH z and a propagation delay of 420ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.