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2020
Journal Article
Title
Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration
Abstract
SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.
Author(s)
Engelmann, Hans-Jürgen
Helmholtz-Zentrum Dresden-Rossendorf, Bautzner Landstraße 400, D-01328, Dresden, Germany
Heinig, Karl-Heinz
Helmholtz-Zentrum Dresden-Rossendorf, Bautzner Landstraße 400, D-01328, Dresden, Germany