Analysis and Design of Output Driver for the Bunch of Wire standard for 16 Gbps data rate in 16 nm FinFET TSMC technology

Multi-Chip Modules (MCM) have become more popular as a result of technology scaling since they are more affordable, require less power, take up less space, and can integrate multiple technologies. However, MCMs require a high-speed
communication network for data transmission. These transceiver systems must be power and area efficient because a failure to do so could negate all the advantages of MCMs over System-on-Chip (SoC). Driver is a circuit in the transmitter that are responsible for driving the data to the receiver through a channel. The drivers are the most power-hungry blocks, and they determine the performance and power efficiency of the transmitter. This thesis aims to design an output driver that complies with the existing industry standards for effective data transfer and uses more recent technological advancements to support compact design methods. This thesis thoroughly examines the interfacing methods and analyses the driver circuit, outlining the advantages and disadvantages of various topologies. The behavioral modelling of the driver provides insight into the circuit’s behaviour. Mathematical calculations support the driver’s transistor-level implementation, and the post-layout results determine the effect of parasitics on the designed circuit. This thesis presents a design of an NMOS-based Voltage Mode diver with a Single-Ended signaling scheme. The driver is designed to meet the Bunch of Wire (BoW) standard requirements using 16 nm FinFET TSMC technology. The design operates reliably at a data rate of 16 Gbps exhibiting an energy efficiency of 0.288 pJ/bit and a voltage swing of 0.4 V. Additionally, the design achieved -16.83 dB return loss performance and jitter of
0.113 UI. The designed driver has a chip size of 0.000672 mm2.