Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

In this paper, the electrical characterizations of a 4H-SiC CMOS NOT logic gate are performed in the temperature range from 300K down to 100K and the results are analyzed. The integrated circuit is fabricated with the Fraunhofer IISB 4H-SiC 2µm CMOS technology and the lateral NMOSFET and PMOSFET have channel form factor of 6/6 and 44/6, respectively. The circuit is supplied with a 20V. The curves show a reduction of the threshold voltage from 8.96V to 6.85V reducing the temperature from 300K to 100K and an ever-widening region in the High side (NMOSFET in saturation and PMOSFET in triode regime) compared to the Low side (NMOSFET in triode and PMOSFET in saturation regime). However, the noise margins are still wide enough for practical applications, making the circuit still useful. The behavior can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. Finally, analysis also focuses on the power dissipation during the transition of the output voltage from high (low) to low (high).