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  4. UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale
 
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2008
Poster
Titel

UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

Titel Supplements
Poster at MNE 2008, 34th International Conference on Micro and Nano Engineering, Athens, Greece
Alternative
Prozessoptimierung für die UV Nanoimprint Lithografie zur Herstellung nanoskaliger elektronischer Bauelemente
Author(s)
Schmitt, H.
Amon, B.
Petersen, S.
Rommel, M.
Bauer, A.J.
Ryssel, H.
Konferenz
International Conference on Micro- and Nano-Engineering (MNE) 2008
DOI
10.24406/publica-fhg-359320
File(s)
003.pdf (2.75 MB)
Language
English
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Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB
Tags
  • UV nanoimprint lithography

  • residual layer

  • electron device

  • UV curing material

  • MOSFET

  • transistor

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