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  4. Modeling and synthesis of communication subsystems for loop accelerator pipelines
 
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2010
Conference Paper
Title

Modeling and synthesis of communication subsystems for loop accelerator pipelines

Abstract
The communication synthesis for data transfer and synchronization between loop accelerators is a major challenge in streaming applications. The complexity of the problem arises from the fact that optimal memory mapping and address generation in communication subsystems for parallel data access and out-of-order communication depend on tiling and scheduling choices. This paper solves the problem of communication synthesis by leveraging the windowed synchronous data flow (WSDF) model for communication synthesis. In this context, an intermediate representation of communicating loops in the polyhedral model and a unified methodology for their projection onto the WSDF model is proposed. Finally, we present the architecture template, synthesis methodology, and overhead of the communication primitive.
Author(s)
Dutta, H.
Hannig, F.
Schmid, M.
Keinert, J.
Mainwork
21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010  
Conference
International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2010  
DOI
10.1109/ASAP.2010.5540760
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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