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  4. Adaptive High Density RDL Technologies for Panel Level Packaging
 
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2021
Journal Article
Title

Adaptive High Density RDL Technologies for Panel Level Packaging

Abstract
Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC substrates based on large formats (up to 600 x 600 mm<sup>2),</sup> known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. This paper will show the development of 5µm L/S RDL routing density and chips with 50µm bump pitch. Here, the 6x6 mm<sup>2</sup> dies are symmetrically embedded into an organic laminate matrix. A PCB core (100µm thickness) with a very low coefficient of thermal expansion (CTE) containing laser cut cavities is used, acting as a frame layer. Besides mechanical and handling stability, the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame, the dies are embedded by lamination of an organic build-up film with 25µm thickness equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here a strong focus is set on RIE etching of the polymer material. Highly accurate measurement of the real die position is essential for the following processing. The formation of the redistribution layer (RDL) is done in a semi-additive process (SAP) utilizing sputtering technique and direct imaging (LDI). To achieve the fine pitch demands, an adaptive imaging process is applied. Therefore, a newly developed LDI machine is used to write structures in a 7µm photoresist. This exposure also combines the measurement data of the real die position and the adaption of the exposure artwork, in order to achieve the highest registration quality. The next step in development will target achieving 2µm L/S structure size. First steps toward this goal will be addressed briefly.
Author(s)
Boettcher, Lars  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Kosmider, Stefan  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Schein, Friedrich Leonhard
Technische Universität Berlin
Kahle, Ruben  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Ostmann, Andreas  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Journal
Advancing Microelectronics  
Funder
Fraunhofer-Institut für Zelltherapie und Immunologie  
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Keyword(s)
  • 3D system in package

  • adaptive imaging

  • direct imaging

  • IC substrate

  • panel level packaging

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