An optimized architecture for a rapid-prototype-emulator

An ASIC prototype based on field programmable gate-arrays (FPGA) is a fast and cheap alternative to a silicon based prototype for design verification. To meet the high performance and complex functionality of the digital part of ASICs, it is necessary to connect FPGAs to an array. The connection-structure determines the realtime ability and the variety of designs that can be implemented into the FPGA-array. A new architecture for the connection structure of FPGAs as the base for a rapid-prototype emulation-system is presented. This architecture leads in relation to conventional systems to a better usage of the FPGAs and to an emulation-timing close to realtime in most designs.