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  4. Embedded self repair by transistor and gate level reconfiguration - possibilities and limitations
 
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2006
Conference Paper
Title

Embedded self repair by transistor and gate level reconfiguration - possibilities and limitations

Other Title
Eingebettete Selbstreparatur durch Rekonfiguration auf Transistor- und Gatterebene - Möglichkeiten und Grenzen
Abstract
Technology forecasts predict that nanometer IC technologies will not yield large chip areas without non-functional transistors. Mechanism of redundance and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits.
Author(s)
Kothe, R.
Brandenburg University of technology Cottbus
Vierhaus, H.T.
Brandenburg University of Technology Cottbus
Coym, T.
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Vermeiren, W.
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Straube, B.
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Mainwork
9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems 2006. Proceedings  
Conference
Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 2006  
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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