EMC modeling and simulation on chiplevel

Due to increasing demands for reduced electromagnetic emission on chip-level in combination with more complex circuits and faster design cycles, it is mandatory to spend effort on EMC models and simulation for chip design. In this paper a three-level approach, based on (1) testchip design and measurement, (2) RLC-extraction of supply system plus transistor netlist simulation, (3) behavioural models for simple gates and complex digital modules will be presented. Correlation between results of those three levels has to be established, and finally behavioural models for complete CMOS VLSI chips have to be derived and implemented in a simulation environment.