Impact of mechanical strain on 22 nm FDSOI device performance using nanoindentation

A novel nanoindentation technique is used to investigate the influence of mechanical strain on integrated circuit performance. The approach aims to investigate localized stress fields caused by Chip-package interaction and resulting reversible transistor parameter deviations due to the piezoresistive effect. Nanoindentation enables controlled localized loads with high lateral precision and to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in the 22 nm FDSOI technology node enable a high sensitivity to mechanical load. They were used to monitor the strain effect on the transistors performance. Complementary FEM simulations provide deeper insight into the occurring stress tensor components and their respective impact. The results give an estimation for package related stress influences on devices based on the established correlation of mechanical load/strain and devices performance.