Automatic footprint compaction and bond wire placement for bare die chips stacks

When designing a SiP with multiple stacked chips as bare die, the SiP designer has to design the substrate footprints of his chip stacks on his own. He needs detailed knowledge of the chip stacking and wire bonding processes and the design rules. Furthermore, he needs to prevent multiple time consuming design iterations. The Paper presents an automatic algorithm which creates a drc valid substrate footprint for a given set of bare die chip stacks. Closing this gap with EDA-tools is an important factor to push this technology.