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  4. IISB2 Topology for 48 V to 1 V Point of Load Applications
 
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2025
Conference Paper
Title

IISB2 Topology for 48 V to 1 V Point of Load Applications

Abstract
By using an integrated, galvanically isolated, separated buck/boost topology (short iisb<sup>2</sup> topology) a high efficiency 48 V to 1 V Point of Load (PoL) unit is demonstrated. This paper describes why the proposed topology can be even useful in typical non-insulated DC/DC applications, like processor supplies by deducing the proposed topology from the well-known single stage hard-switched half-bridge with current doubler rectifier topology. Moreover, it will be shown why the special requirements for processor PoL applications can be easier fulfilled by the proposed topology.
Author(s)
Zeltner, Stefan  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Hager, Jan
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Seliger, Bernd
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Ayllon, Gerson
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Haager, Daniel
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Eckardt, Bernd
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Mainwork
Pcim Europe Conference Proceedings
Funder
Bundesministerium für Bildung und Forschung  
Conference
2025 International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2025
DOI
10.30420/566541078
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
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