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  4. SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2
 
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2020
Conference Paper
Titel

SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2

Abstract
This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO 2 -based 1T1C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ Hf 0.5 Zr 0.5 O 2 (HZO)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization, 2P T > 40 mC/cm 2 endurance > 10 11 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of 2.5 V and operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.
Author(s)
Okuno, J.
Kunihiro, T.
Konishi, K.
Maemura, H.
Shute, Y.
Sugaya, F.
Materano, M.
Ali, T.
Kuehnel, K.
Seidel, K.
Schroeder, U.
Mikolajick, T.
Tsukamoto, M.
Umebayashi, T.
Hauptwerk
IEEE Symposium on VLSI Technology 2020. Proceedings
Konferenz
Symposium on VLSI Technology 2020
Thumbnail Image
DOI
10.1109/VLSITechnology18217.2020.9265063
Language
English
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Fraunhofer-Institut für Photonische Mikrosysteme IPMS
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