• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Artikel
  4. Monitoring cache behavior on parallel SMP architectures and related programming tools
 
  • Details
  • Full
Options
2005
Journal Article
Title

Monitoring cache behavior on parallel SMP architectures and related programming tools

Abstract
This paper describes the ideas and developments of the project EP-CACHE. Within this project new methods and tools are developed to improve the analysis and the optimization of programs for cache architectures, especially for SMP clusters. The tool set comprises the semi-automatic instrumentation of user programs, the monitoring of the cache behavior, the visualization of the measured data, and optimization techniques for improving the user program for better cache usage. As current hardware performance counters do not give sufficient user relevant information, new hardware monitors are designed that provide more detailed information about the cache utilization related to the data structures and code blocks in the user program. The expense of the hardware and software realization will be assessed to minimize the risk of a real implementation of the investigated monitors. The usefulness of the hardware monitors is evaluated by a cache simulator.
Author(s)
Brandes, T.
Schwamborn, H.
Gerndt, M.
Jeitner, J.
Kereku, E.
Schulz, M.
Brunst, H.
Nagel, W.
Neumann, R.
Müller-Pfefferkorn, R.
Trenkler, B.
Karl, W.
Tao, J.
Hoppe, H.-C.
Journal
Future generation computer systems : FGCS  
DOI
10.1016/j.future.2004.09.005
Language
English
Fraunhofer-Institut für Algorithmen und Wissenschaftliches Rechnen SCAI  
Keyword(s)
  • hardware cache monitoring

  • performance analysis

  • cache optimization

  • parallel programming tool

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024