Managing stress-induced effects on performance and reliability of 3D IC stacks

The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV stacking technology. It requires the determination of a set of accurate materials data, for wafer-level and package-level structures, needed to feed a materials database that comprises the input parameters for simulation. Particularly the generation of materials data such as (local and effective) Young's modulus, Poisson ratio and (effective) coefficients of thermal expansion (CTE) on several scales will be described. Particularly for sub-mm structures, materials properties change depending on the size of the structure. For some materials, especially the materials used in packaging, these characteristics are a non-linear function of temperature, i. e. temperature-dependent materials data have to be determined. For polycrystalline materials, their microstructure has to be considered. Eventually, local stress measurements are needed for model validation and calibration, to determine the effect of the TS V/package-induced stress on the transistor performance and reliability. Due to the high resolution needed, the only direct technique to measure strain in transistor channels is TEM.