Dr.-Ing.

Braun, Tanja

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  • Publication
    A Closer Look to Fan-out Panel Level Packaging
    ( 2023)
    Braun, Tanja
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    Hölck, Ole
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    Voitel, Marcus
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    Obst, Mattis
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    Voges, Steve
    ;
    Becker, Karl-Friedrich
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    Aschenbrenner, Rolf
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    Schneider-Ramelow, Martin
    Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face-down have reached maturity and are introduced in high volume manufacturing. This paper discusses warpage in detail as one key challenge in fan-out packaging and how to influence the warpage during processing of a reconfigured panel for Chip first / RDL last approach.
  • Publication
    Presentation of a Reliable Molded Power-PrePackage
    ( 2022)
    Thomas, Tina
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    Rämer, Olaf
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    Nguyen, Thanh Duy
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    Hoene, Eckart
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    Braun, Tanja
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    Liu, Chunlei
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    Pavliček, Niko
    Present paper introduces a package alternative to commercially available single power chips, embedded into printed circuit boards on chip scale size. It addresses assembly and interconnect technology for power electronic devices, namely the packaging of bare power dies into a robust package with superior thermal performance and reliability. Use of Cu columns as top side contact and isotropic encapsulation material enable highly reliable packages with thermal path on bottom and top side. The study investigates the feasibility of applied assembly and encapsulation processes regarding mass production. Package reliability has been evaluated by Active Power Cycling and Moisture Sensitivity Level tests.
  • Publication
    Mold based D-band slotted SIW bandpass filter
    ( 2022)
    Chernobryvko, Mykola
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    Kanitkar, Abhijeet Mohan
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    Müller, Friedrich
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    Schwanitz, Oliver
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    Ndip, Ivan
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    Schneider-Ramelow, Martin
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    Murugesan, Kavin Senthil
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    Braun, Tanja
    D-band substrate integrated waveguide (SIW) bandpass filter with slots based on mold compound was manufactured and measured. The investigation shows the high potential of SIW filters to be integrated in packages using fan-out wafer level packaging (FOWLP). The manufactured sample was inspected using microscope to validate the measurements. The second order filter configuration demonstrates good selectivity properties. The measurements and full-wave modelling demonstrate a very good correlation in terms of magnitude and phase of return and insertion losses.
  • Publication
    Fan-out Wafer Level Packaging of GaN Traveling Wafer Amplifier
    ( 2022)
    Schwantuschke, Dirk
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    Ture, Erdin
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    Braun, Tanja
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    Nguyen, Thanh Duy
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    Wöhrmann, Markus
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    Pretl, Michael
    ;
    Engels, Sven
    This paper presents a Fan-out Wafer Level Packaging technology, which was developed to package a GaN-based Traveling Wafer Amplifier. The innovative packaging approach embed the broadband high-power amplifier in an epoxy molding compound. The Fan-out package includes an in-package Cu-based heatsink which is directly attached to the metalized chip backside. S-parameter measurements raised from a realized demonstrator yield a linear gain of 10 dB in DC-pulsed and 8 dB in continuous wave operation, along with a bandwidth of 15 GHz. Large-signal measurements of the demonstrator result in a saturated output-power of more than 33 dB (2 W), along with a maximum power added efficiency of 10 %.
  • Publication
    High-Resolution Printing of Redistribution Layers for Fan-Out Wafer-Level Packaging by using Ultra-Precise Micro-deposition Technology
    ( 2022)
    Roshanghias, Ali
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    Dreissigacker, Marc
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    Grądzka-Kurzaj, Iwona
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    Binder, Alfred
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    Schneider-Ramelow, Martin
    ;
    Witczak, Łukasz
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    Braun, Tanja
    Implementing Additively Manufactured Redistribution Layers (AM-RDL) for Fan-Out Wafer-Level Packaging (FOWLP) has spurred interest recently. Especially for MEMS FOWLP, where the standard fabrication of RDLs faced challenges to provide conformity to 3D topographies or protecting delicate structures, AM-RDLs can be regarded as the most promising approach. The state-of-the-art AM RDLS (e.g. inkjet printed) are lagging way behind the lithography-based ones due to inferior feature sizes (i.e. higher line/ space or high pitch interconnects). To address this bottleneck, in this study a recently-developed Ultra-Precision Deposition (UPD) technology was utilized to print high-resolution RDLs. By optimizing UPD printing parameters, such as printing pressure, nozzle size, nozzle movement and speed, ultra-fine silver (Ag) and polyimide features were extrusion printed. Here, molded daisy chain chips were used as test samples, on which ultra-fine Ag RDLs with an average width of 6.5 μm and thickness of 2.7 μm were printed successfully. Electrical test and cross-sectional analysis verified line continuity and full out-of-plane offset (Z-step) coverage at the chip/ epoxy molding compound (EMC) interface. Additionally, multilayering of printed layers for high-density FOWLP was demonstrated.
  • Publication
    Panel Level Packaging - Where are the Technology Limits?
    ( 2022)
    Braun, Tanja
    ;
    Hölck, Ole
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    Obst, Mattis
    ;
    Voges, Steve
    ;
    Kahle, Ruben
    ;
    Böttcher, Lars
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    Billaud, Mathilde
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    Stobbe, Lutz
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    Becker, Karl-Friedrich
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    Aschenbrenner, Rolf
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    Voitel, M.
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    Schein, F.-L.
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    Gerholt, L.
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    Schneider-Ramelow, M.
    Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face- down have reached maturity and are introduced in high volume manufacturing. For Fan-out Wafer Level Packaging (FOWLP) clear application trends and technology roadmaps do exist. These range from low density core technology for e.g. RF or PMIC (power management IC) packaging over high density application processor packaging to ultra-high-density applications for networking servers etc.. For panel level packaging it is still not fully clear if the same performance can be achieved as on wafer level as larger process / panel sizes may have higher challenges in process control, accuracy and consistency, material and equipment or handling.Main driver for moving to panel level packaging is of course lowering the packaging cost. More packages can be processed in parallel and panel formats have a much better area utilization (ratio between panel/wafer size and package size) than round wafer shapes. Also, environmentally PLP is advantageous by e.g. lower waste and smaller carbon footprint. However, for both aspects processes with sufficiently high yield are required. This is especially true for FOWLP/PLP RDL last processes as a failure in the RDL will also lead to a loss of packaged die(s).This paper describes current technology developments to access the limits of the panel level packaging technology. Warpage, die shift and fine line capabilities are the main topics here. To better understand the compression molding process as the technological basis of the reconfigured panel and its influence on warpage and die shift a dedicated sensor mold tool has been developed. By integration of temperature, pressure, dielectric and fiber Bragg grating sensors the flowing and curing behavior of epoxy molding compound can be studied in-situ. Results will support process simulations for warpage prediction and more accurate die shift compensation.For large panel processing an adaptive patterning approach might be needed anyhow to achieve a high yield. Here the combination of an intelligent assembly strategy for high speed and sufficient accuracy, capabilities to measure each die position and a maskless lithography process adapting the redistribution layer (RDL) to each die position may lead to a cost-effective high yield process.In addition, a clear trend towards finer lines and spaces as well as smaller via diameters is also demanded for large panel RDL processes. Process developments towards 2 μm lines and spaces and via shrinking on 610x457 mm2 (24'x18') panels are shown including material and process options.In summary this paper will show current PLP technology developments for future high-end applications and will cover at the same time economic and environmental aspects.
  • Publication
    Multiscale warpage behaviour in a Fan-Out Panel during thermal cycles
    ( 2022)
    Hölck, Ole
    ;
    Vernhes, Pierre
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    Gamba, Baptiste
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    Cruz, Rodolfo
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    Huber, Saskia
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    Braun, Tanja
    ;
    Schneider-Ramelow, Martin
    In this work, the warpage of a panel in the context of fan-out packaging is analysed. On a panel size of 300 × 300 mm2 a die layout is molded and debonded from the temporary carrier. The resulting warpage is characterised temperature dependent using the Projection Moiré technique globally across the complete panel and locally on the scale of few dies. Globally, results are analysed with respect to the shape change of the warpage and residual warpage after thermal cycling. Locally the curvature of single dies is compared to the global curvature of the tunnel shaped warpage. This work is part of the investigations with the aim to describe and control the warpage effects in Fan-Out Panel Level Packaging.
  • Publication
    Design, Fabrication and Measurement of FOWLP-based Series-Fed Antennas for 6G D-Band MIMO Applications
    ( 2022)
    Le, Thi Huyen
    ;
    Schwanitz, Oliver
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    Ndip, Ivan
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    Mueller, Friedrich
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    Braun, Tanja
    ;
    Schneider-Ramelow, Martin
    In this paper, the development of FOWLP-based antenna arrays for 6G D-Band MIMO applications is presented. The proposed array consists of five patch elements, which are connected to each other to create a 1x5 series fed antenna array. The array was designed, simulated and fabricated on 150 μm mold substrate material at 140 GHz. The amplitude tapering method was applied to the array to suppress the high side-lobes levels. Finally, return loss and radiation patterns radiation of the proposed antenna array were measured and compared with simulated results. Very good correlation between simulation and measurement is obtained.
  • Publication
    Packaging Platform for low to medium Power Packages
    ( 2022)
    Thomas, Tina
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    Nguyen, Thanh Duy
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    Blechert, Martin
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    Hoffmann, Stefan
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    Obst, Mattis
    ;
    Becker, Karl-Friedrich
    ;
    Braun, Tanja
    ;
    Dreissigacker, Marc
    ;
    Schneider-Ramelow, Martin
    In recent years, the molding process gains more and more interest for encapsulation of power related packages. Main driver for the observed trend is the possibility to design very compact packages, offering an improved heat transfer compared to silicone-potted modules with only one thermal path. Present paper describes a platform approach for convenient encapsulation of power devices with epoxy-based encapsulants by Compression Molding, allowing encapsulation of different package designs with only one molding tool. Today, Compression Molding is widely used as encapsulation process of bare dies; present packaging approach shows successful encapsulation of a broader component variety. Present paper addresses process-and application-related requirements for the encapsulation material of power devices.
  • Publication
    BiCMOS Integrated Temperature Sensor for Thermal Evaluation of Fan-out Wafer-level Packaging (FOWLP) including Hot Spot Analysis
    ( 2022)
    Wietstruck, Matthias
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    Mausolf, Thomas
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    Lehmann, Jens
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    Cao, Zhibo
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    Nguyen, Thanh Duy
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    Wöhrmann, Markus
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    Braun, Tanja
    A SiGe BiCMOS thermal chip for thermal package characterization is developed and demonstrated together with a chip-first, face-down FOWLP technology. The dedicated BiCMOS thermal chip enables a spatially resolved heat generation and temperature characterization to analyze the effects of uniform heat generation as well as hot spots within integrated circuits and package technologies. The BiCMOS thermal chip can be applied for various wafer-level package technology providing an in-depth analysis of the thermal management.