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Patent
Title
Halbleiteranordnung und Verfahren zu deren Herstellung
Other Title
Semiconductor arrangement for e.g. mobile communication application, has condenser connected with integrated circuit and designed as monolithic deep structure with trench on rear side of substrate
Abstract
(A1) Die Erfindung beschreibt eine Halbleiteranordnung und Verfahren zur Herstellung derselben, wobei die Halbleiteranordnung mit einer auf einem Substrat (1) angeordneten integrierten Schaltung (2) versehen ist, wobei die integrierte Schaltung (2) auf der Vorderseite des Substrats strukturiert ist und mindestens ein Kondensator (20) mit der integrierten Schaltung verbunden ist, dadurch gekennzeichnet, dass der mindestens eine Kondensator auf der Rueckseite des Substrats (1) als monolithische Tiefenstruktur mit mindestens einem Graben (3) ausgebildet ist.
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DE 102007009383 A1 UPAB: 20080912 NOVELTY - The arrangement has an integrated circuit (2) arranged on a substrate (1) and structured on a front side of the substrate. A condenser (20) is connected with the integrated circuit and is designed as a monolithic deep structure with a trench (3) on a rear side of the substrate. The trench has a depth and a width, and a ratio of the depth to width amounts between 60 to 1 and 30 to 1. The trench has side walls (31, 32) that form an angle in the range between 45 and 90 degrees with planar surfaces (33, 34) of the substrate. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method of manufacturing a semiconductor arrangement. USE - Semiconductor arrangement for use in a mobile communication application, microcontroller and digital signal processor. ADVANTAGE - The condenser is arranged on the rear side of the substrate, so that the condenser can be automatically provided in the integrated semiconductor component, thus reducing the size of the component of the semiconductor chip and achieving better buffer performance based on the small distance to the circuit arrangement on the opposite side of the substrate, and hence reducing the space requirement of the semiconductor arrangement. The condenser is designed as the monolithic deep structure, so that the structure can be increased to a multiple for the condenser surface opposite to the planar structure to provide the surface enlargement and the condenser can be economically manufactured, thus economically achieving high capacity to the closest area required for backup- and/or buffer condenser to hold the voltage peaks, without requiring passive backup capacitors.
Inventor(s)
Marenco, N.
Patent Number
102007009383
Publication Date
2007
Language
German