Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    A Novel Quantitative Adhesion Measurement Method for Thin Polymer and Metal Layers for Microelectronic Applications
    ( 2022)
    Woehrmann, Markus
    ;
    Mackowiak, Piotr
    ;
    Schiffer, Michael
    ;
    Lang, K.-D.
    ;
    Schneider-Ramelow, M.
    Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface's fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.
  • Publication
    Investigation of Deep Dry Etching of 4H SIC Material for MEMS Applications Using DOE Modelling
    ( 2021)
    Erbacher, K.
    ;
    Mackowiak, P.
    ;
    Schiffer, M.
    ;
    Lang, K.-D.
    ;
    Schneider-Ramelow, M.
    ;
    Ngo, H.-D.
    In this paper the reactive ion etching (RIE) of 4H silicon carbide (SiC) with an SF 6 /O 2 /He gas mixture is investigated in an inductively coupled plasma etcher (ICP). Objective is the analysis of the manufacturing process of a SiC diaphragm for a bulk micromechanical pressure sensor, by etching a cavity into silicon carbide wafer. In addition, the selectivity of etching masks made from Nickel and Copper against SiC are examined. By means of Design of Experiments (DOE) in the software JMP, a test series with 29 recipes is set up. The process is varied over the parameters chamber pressure, source power, platen power, SF 6 flow rate, O 2 flow rate, clamp cooling and mask material. To evaluate the etched samples quantitatively, cross sections of 29 specimens are made. The results are used to create a mathematically model for the prediction of etching rate, profile angle and occurring micro masking. The model is evaluated by etching samples. Etching a cavity with an opening width of 800 mm to a depth of 300 mm with a maximum etching rate of 4 mm/min, vertical profile walls and a smooth and even etched base is demonstrated. The selectivity of the modelled process is 115 compared to Cu, the observed selectivity of Cu is higher compared to Ni.
  • Publication
    RF Modeling and Measurement of a Novel Aperture-Coupled Hybrid Glass-Silicon 5G Antenna Array
    ( 2021)
    Le, T.H.
    ;
    Rossi, M.
    ;
    Ndip, I.
    ;
    Kaiser, M.
    ;
    Manier, C.-A.
    ;
    Gernhardt, R.
    ;
    Oppermann, H.
    ;
    Lang, K.-D.
    ;
    Reichl, H.
    In this work, the electromagnetic modelling and measurement of a novel aperture-coupled hybrid glass-silicon 1x2 antenna array is presented. The patch elements are located under a glass substrate, which is placed on a silicon layer. The antenna array is fed using aperture coupling. A cavity is etched in the silicon layer to reduce the impact of silicon, and thus ensures significant improvement of the antenna efficiency and gain. The proposed antenna was fabricated and measured. Very good correlation is obtained between simulation and measurement.
  • Publication
    Influence of Ball Size and Geometry on the Reliability and RF Performance of mmWave System-in-Package: A Simulation Approach
    ( 2021)
    Dilek, S.
    ;
    Ndip, I.
    ;
    Rossi, M.
    ;
    Tschoban, C.
    ;
    Kuttler, S.
    ;
    Wittler, O.
    ;
    Lang, K.-D.
    ;
    Goetze, C.
    ;
    Berger, D.
    ;
    Wieland, M.
    ;
    Schneider-Ramelow, M.
    Solder ball reliability is a long-discussed topic in microelectronic packaging. With new package types needed for mmWave applications a trade-off between reliability and RF performance may arise, when the solder ball geometry has to be selected for specific package assemblies. In this work, the lifetime for different solder ball geometries is investigated within a numerical simulation workflow, by means of a sensitivity analysis in which the ball diameter, pad sizes and stand-off distance are varied. Next to lifetime estimations, 3D full-wave simulations have been applied to analyze the RF performance of the structures under investigation at 77-79 GHz (E-band) center frequencies relevant for automotive radar applications. Finally, the trade-off between RF performance and reliability is illustrated and quantified.
  • Publication
    Dry Etched through SiC Via (TSiCV) Process Analysis Using DOE Modeling
    ( 2020)
    MacKowiak, P.
    ;
    Schiffer, M.
    ;
    Scheider-Ramelow, M.
    ;
    Lang, K.-D.
    This paper describes the research on modelling the etching parameters of SiC using RIE. The experiments were performed using a design of experiments (DOE) with a total 78 experiments and D-efficiency of over 85.4 finding the most significant process parameters impacting the etch result. All experiments were carried out for three different via diameters. The evaluation of the via etching was performed using confocal microscopy and by cross sections of the SiC vias. Afterwards the model was verified with etching experiments show very good match with the prediction model. The deviation between the model and the verification was below 6%.
  • Publication
    Electromagnetic switching cell design and characterization for WBG power semiconductors
    ( 2020)
    Klein, K.
    ;
    Hoene, E.
    ;
    Lang, K.-D.
    This paper presents several approaches to simplify the design and characterization of fast switching power modules. Limits of acceptable parasitic parameters for power module design are obtained by circuit simulation respective to the semiconductor model having properties defined in this paper. Furthermore, this paper gives an overview of the parasitic inductances and capacitances of switching cells and weights their importance for power module with half-bridge topology. By means of this analysis shoot-through while turn-on can be eliminated and unwanted voltage overshoot and oscillations at turn-off can be minimized to required limits. A non-invasive method for the determination of the DC link inductance and its partial stray inductances is shown using standard impedance measurements.
  • Publication
    Cap Fabrication and Transfer Bonding Technology for Hermetic and Quasi Hermetic Wafer Level MEMS Packaging
    ( 2020)
    Zoschke, K.
    ;
    MacKowiak, P.
    ;
    Kröhnert, K.
    ;
    Oppermann, H.
    ;
    Jürgensen, N.
    ;
    Wietstruck, M.
    ;
    Göritz, A.
    ;
    Tolunay Wipf, S.
    ;
    Kaynak, M.
    ;
    Lang, K.-D.
    This article describes a new wafer level capping technology for hermetic or quasi-hermetic 1st level device sealing. The technology is based on fabrication of cap structures with bond frames and optional recesses at temporary carrier wafers and their subsequent transfer bonding to the device wafer. The final release of the caps from the carrier wafer is obtained by laser assisted de-bonding. The cap fabrication relies on deposition and structuring methods from advanced packaging featuring mask aligner lithography for pattern definition. Based on that, bond frames and also the cap outlines can be defined almost freely by layout and thus, fully arbitrary shaped cap structures with irregular forms, sizes and locations and with irregular pitch become possible. The bond frames can be made of adhesive, metal or metal with solder cap to provide just mechanical or air tight device sealing to the target wafer. Since the caps are formed from a wafer, which is bonded to a carrier wafer, even fabrication of ultra-thin caps in the range of 50 μm or less is possible by adding related grinding and polishing steps. For the transfer of the caps to the device wafers, so-called donor wafers are used which can be handled with standard wafer-to-wafer alignment and bonding equipment. Due to the toughness of the temporary adhesive, which holds the caps on the carrier, wafer bonding processes under vacuum with temperatures up to 370 °C and pressures in the MPa range can bet utilized for the cap transfer bonding.The technology was applied for quasi-hermetic sealing of RF-MEMS switches on 200 mm BiCMOS wafers using adhesive bond frames as well as for hermetic sealing operations on 200 mm test wafers and on 200 mm MEMS wafers using soldering of AuSn bond frames. The related cap fabrication and bonding processes as well as associated results are described in this paper.
  • Publication
    Reliability Investigation of Ultra Fine Line, Multi-Layer Copper Routing for Fan-Out Packaging Using a Newly Designed Micro Tensile Test Method
    ( 2020)
    Woehrmann, M.
    ;
    Keller, A.
    ;
    Fritzsch, T.
    ;
    Schiffer, M.
    ;
    Gollhardt, A.
    ;
    Walter, H.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Fan-Out enables new heterogeneous packaging concepts where chips are embedded in an electronic mold compound (EMC) package with ultra-small footprint. These multi-chip systems demand a high routing density in the redistribution layer (RDL) which is realized by fine copper features with line and space structures in the dimension down to 2 mu m, establishing electrical interconnects between the chips across different substrate materials (e.g. silicon chips and mold-filled gaps). The copper lines undergo high mechanical stress due different thermal expansion coefficients of the used materials. Numerous papers investigated reliability topics only focusing on properties of the polymer in the redistribution layer and the solder ball material, but the influence of the mechanical properties of electroplated copper has been a minor topic so far [1] [2] [3].With feature sizes and thicknesses of about 2 mu m, these structures are in the range of copper grain size with the result that different grain structures become more important. Also, the material suppliers start to tune galvanic copper baths to generate e.g. twinned copper structures with mechanically superior behavior. Characterizing these fine structures at that scale is challenging because the properties could be different compared to macro samples. This work presents an on-wafer characterization method of copper features down to 2 mu m with a newly designed wafer scale micro tensile test. This concept allows a test integration in the fab process flow. The elongation at break and the tensile strength of ultra fine line copper lines are measured by the tensile loading. The results are compared with macro scale tensile tests.
  • Publication
    Manufacturing of high frequency substrates as software programmable metasurfaces on PCBs with integrated controller nodes
    ( 2020)
    Manessis, D.
    ;
    Seckel, M.
    ;
    Fu, L.
    ;
    Tsilipakos, O.
    ;
    Pitilakis, A.
    ;
    Tasolamprou, A.
    ;
    Kossifos, K.
    ;
    Varnava, G.
    ;
    Liaskos, C.
    ;
    Kafesaki, M.
    ;
    Soukoulis, C.M.
    ;
    Tretyakov, S.
    ;
    Georgiou, J.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    The proposed work is performed in the framework of the FET-EU project "VISORSURF", which has undertaken research activities on the emerging concepts of metamaterials that can be software programmable and adapt their properties. In the realm of electromagnetism (EM), the field of metasurfaces (MSF) has reached significant breakthroughs in correlating the micro- or nano-structure of artificial planar materials to their end properties. MSFs exhibit physical properties not found in nature, such as negative or smaller-than-unity refraction index, allowing for EM cloaking of objects, reflection cancellation from a given surface and EM energy concentration in as-tight-as-possible spaces.The VISORSURF main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be defined programmatically. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials and will merge the metasurfaces with custom electronic controller nodes at the bottom of the PCB hardware platform. These electronic controllers build a nanonetwork which receives external programmatic commands and alters the metasurface structure, yielding a desired electromagnetic behavior for the Hypersurface platform.This paper will elaborate on how large scale PCB technologies are deployed for the economical manufacturing of the 4-layer Hypersurface PCB hardware platform with a size of 9"x12", having copper metasurface patches on the top of the board and the electronic controllers as 2mmx2mm WLCSP chips at 400mm pitch assembled at the bottom of the platform. The PCB platform designs have stemmed from EM modeling iterations of the whole stack of high frequency laminates taking into account also the electronic features of the controller nodes. The manufacturing processes for the realization of the selected PCB architectures will be discussed in detail.
  • Publication
    A Novel Packaging and System-Integration Platform with Integrated Antennas for Scalable, Low-Cost and High-Performance 5G mmWave Systems
    ( 2020)
    Ndip, I.
    ;
    Andersson, K.
    ;
    Kosmider, S.
    ;
    Le, T.H.
    ;
    Kanitkar, A.
    ;
    Dijk, M. van
    ;
    Senthil Murugesan, K.
    ;
    Maaß, U.
    ;
    Löher, T.
    ;
    Rossi, M.
    ;
    Jaeschke, J.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    In this work, we present a novel packaging and system-integration platform with integrated antennas (antenna-in-package, AiP, platform) for 5G millimeter-wave (mmWave) systems. We illustrate the application of the platform for the development of miniaturized, scalable, low-cost and high-performance 5G mmWave systems for new radio (NR) base stations. RF characterization of the dielectric material of the platform and the integrated mmWave antennas as well as thermal investigations of the platform are presented. The process steps required for the fabrication of the platform are discussed, and an example of a mmWave chip embedded in the platform is shown.