Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Alternative solders for flip chip applications in the automotive environment
    ( 1998)
    Jung, E.
    ;
    Heinricht, K.
    ;
    Klöser, J.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    In addition to Pb toxicity, there are other problems with SnPb solders. In automotive applications, where solder joints are subjected to thermal cycles, severe vibrations, sustained temperatures up to 150 degrees C and peak temperatures of 180 degrees C, the critical failure mode of eutectic SnPb solder in assemblies is bump fatigue. For flip chip technology, induced thermal stresses and strains in solder joints are very hazardous. This paper presents a flip chip process based on electroless Ni/Au bumping and stencil printing of solder paste on wafers. Chemical nickel plating combined with solder printing is a very flexible and cost effective bumping method. The basic process steps and key aspects of this technology are described in detail. Experimental results for an ultra fine pitch printing technique on wafers are shown, and reflowed solder bumps are characterized for uniformity and strength. In comparison to eutectic SnPb, SnBiCu, SnAg, SnCu, and AuSn solder alloys are selected and investigated. The alloys are compared for flip chip technology applicability, microstructure and phase compositions are presented. Microstructure coarsening and phase growth after thermal aging are also investigated. In order to investigate substrate material CTE effects on reliability, flip chip assembly was performed on low temperature cofired ceramic (LTCC) and FR-4 substrates. The flip chip joint quality was investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling with and without underfill on both types of substrate materials are presented.
  • Publication
    Quality and yield of ultra fine pitch stencil printing for flip chip assembly
    ( 1998)
    Heinricht, K.
    ;
    Klöser, J.
    ;
    Lauter, L.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    ;
    Wolter, A.
    Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) with regard to quality and yield. A software tool for design of the stencil layout was developed and the predicted bump heights were compared to the experimental results. In the first part of the paper, a low cost bumping method for flip chip technology is described in detail. This technology is based on chemical Ni/Au deposition on wafers. For solder bumping on wafers, the key aspects of solder paste printing with optimized printable apertures are described and the printing results are presented. The second part of this paper is a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly.
  • Publication
    Reliability aspects of molded BGA's related to material properties
    ( 1998)
    Ehrlich, R.
    ;
    Becker, K.-F.
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    Badri Ghavifekr, H.
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    Ansorge, F.
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    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Sawai, K.
    ;
    Tanaka, A.
    ;
    Kumano, K.
    ;
    Tenya, Y.
    ;
    Chichon, M.
    ;
    Hosokawa, H.
    BGA packages have become increasingly popular for microprocessor device packaging and MCM assembly. This is due to the advantages the ball grid array offers with regard to high lead count combined with large pitches, processable with standard SMT equipment. For BGA package encapsulation, epoxy resins are mostly used, either as glob top or molding compound. For cost effective encapsulation of large numbers of BGA packages, the transfer mold process offers various advantages. The process is fully automated with short process times and the molding compound glass transition temperature (Tg) is very high (>200 degrees C) compared to glob top encapsulants ( 160 degrees C) offering higher reliability at elevated temperatures. However, BGA packages challenge both material suppliers and packagers as this package type is asymmetric and is thus very sensitive to encapsulant material properties. Properties to consider are reduced encapsulation material shrinkage after molding to provide low warpage, and optimized molding compound adhesion to the materials present in a BGA to avoid delaminations that might cause electrical failures. Fraunhofer IZM and Toshiba Chemical have designed test vehicles to investigate different BGA molding compounds with regard to substrate adhesion with various types of solder resist after molding and after package reliability testing. Results of these investigations are reported and investigations regarding humidity sensitivity (according to JEDEC Std. 020) of the encapsulated BGA and the relationship between adhesive strength of EMC to solder mask and humidity uptake of the package are described.
  • Publication
    The development of a modular 32 Bit microcontroller MCM in top bottom BGA (TB-BGA) technique
    ( 1998)
    Leutenbauer, R.
    ;
    Amiri Jam, K.
    ;
    Reichl, H.
    A modular 32-bit microcontroller MCM is described, that takes advantage of the TB-BGA technique developed by IZM. By using a pin compatible BGA configuration at the bottom and the top of the MCM carrier, a 3D stack assembly of several TB-BGAs is possible. The existing ceramic TB-BGAs form a 16 bit controller family, consisting of microcontroller, memory and interface modules. A full operating 16 bit processor unit requires a volume of only 1.2 cm3. Considering thermomechanical reliability, the compact stack assembly reduces bending loads and shear forces by using suitable materials. The solder ball area configuration ensures a good thermal conductivity.
  • Publication
    Correlation of thermo-mechanical properties of adhesives with reliability of FC interconnections
    ( 1998)
    Mießner, R.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    This paper presents an evaluation of isotropic and anisotropic conductive adhesives for flip chip applications. Samples consist of bumped test chips mounted on fine pitch rigid and flexible substrates. The finest pitches are 150 mu m for rigid FR4 substrates and 100 mu m for flex substrates. Isotropic conductive adhesives are promising candidates for adhesive joining. As they conduct electricity equally in all directions, the material must be applied precisely to the points to be connected, and not allowed to flow and short circuit between circuit lines. Anisotropic conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix. The concentration assures reliable conductivity between substrate and IC electrodes but insulation between adjacent bumps. Several adhesives, both commercial and experimental products, were investigated. A detailed thermo-mechanical analysis was used to characterize the materials according to their physical properties. This analysis method was also used to optimize the curing profile, i.e. to shorten curing time. The reliability evaluation was performed with special regard to the degradation and to interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. Reliability test data was correlated with the thermo-mechanical properties. We thus derived simple criteria for adhesive selection for flip chip applications.
  • Publication
    Implementation of flip chip technology into volume manufacturing demonstration of processes
    ( 1998)
    Jung, E.
    ;
    Heinricht, K.
    ;
    Kutzner, K.
    ;
    Klöser, J.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Brommelhaus, A.
    Until now, use of flip chip technology has not been widespread in volume manufacturing, although it provides a number of significant advantages over standard surface mount devices. In particular, the cost aspect of using flip chip technology in a large scale manufacturing environment is expected to overcome the remaining issues. In order to illustrate the equipment and processes involved for incorporation of flip chip attachment into a production process, a demonstration center was established at FhG-IZM. Critical process steps were identified and addressed. This article gives a detailed insight into the actual implementation of a flip chip process into a SMD compatible production line, highlighting aspects of bump provision, cleaning, chip placement and underfilling. Bumping covers low cost processes such as electroless nickel as under-bump metallization (UBM) and stencil printed solder deposits using advanced printing technology. The necessity of cleaning and the key aspects for achievement of high reliability with industrial applied processes is highlighted. Required features of the placement machine and related critical issues are presented. Underfill application is also covered, focussing on important aspects for process optimization.
  • Publication
    Thermo-mechanical reliability of flip chip structures used in DCA and CSP
    ( 1998)
    Schubert, A.
    ;
    Dudek, R.
    ;
    Vogel, D.
    ;
    Michel, B.
    ;
    Reichl, H.
    The continuing demand towards high-density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology and chip size packages (CSP). The advantages in density, cost and electrical performance are obvious. Solder joints, the most widely used flip chip interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. This causes high thermally induced creep strain on the interconnects during temperature cycling and leads to early failure of the solder connections. The reliability of flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. However, over ranges of design, process, and material parameters, different failure modes are observed with significant dependence on material properties and geometry. Nonlinear finite element analysis for flip chip structures is carried out to investigate the reliability impact due to a number of selected design and material parameters. Especially two fundamental issues are addressed, namely, the optimization of thermomechanical properties of underfill materials and manufacturing process-induced defects.
  • Publication
    Characterization of adhesive materials for high circuit density applications
    ( 1998)
    Aschenbrenner, R.
    ;
    Mießner, R.
    ;
    Becker, K.-F.
    ;
    Reichl, H.
    This report presents the results of the evaluation of isotropic and anisotropic conductive adhesives for flip chip and chip size package applications. Samples consist of bumped testchips mounted on fine pitch rigid and flexible substrates. The finest pitch of the rigid glass substrates is 70 mu m and for the flexible substrates 100 mu m. Promising candidate for adhesive joining technique are the isotropic conductive adhesives. These adhesives are isotropic, which means that they conduct electricity equally in all directions. To use such adhesives in flip chip applications, the material has to be applied precisely onto the points to be connected, and is not allowed to flow and short circuit between circuit lines. The anisotropicaliy conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix at a concentration that is high enough to assure reliable conductivity between the substrate and the IC electrodes. The reliability evaluation was performed with special regard to the degradation and to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. A detailed thermo-mechanical analysis was used to determine the optimal cure schedule and to characterize the materials according to their physical properties. This kind of analysis method has also been used to optimize the curing profile, i.e. to shorten the curing time.
  • Publication
    Reliability investigations of Sn/Pb and lead free solders for flip chip technology
    ( 1998)
    Klöser, J.
    ;
    Jung, E.
    ;
    Heinricht, K.
    ;
    Kutzner, K.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    This paper presents a flip chip technique based on electroless Ni-Au bumping and stencil printing of solder paste on wafers. The process steps and key aspects are described in detail. Experimental results for an ultra fine pitch printing technique on wafers are shown and reflowed solder bumps are characterized in terms of uniformity and strength. In comparison to eutectic SnPb solder, five alloys (BiSn, SnBiCu, SnAg, SnCu, AuSn) are investigated. In the second part of the paper, a comparison of solder alloy properties for applicability to flip chip technology, microstructure evaluation and phase compositions are presented. Microstructure coarsening and phase growth after thermal aging are also investigated. In order to assess the effect of substrate CTE on reliability, flip chip assembly was performed on LTTC and FR-4 substrates. Flip chip joint quality was investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, joint reliability results after thermal cycling with and without underfill on both substrate types are presented.
  • Publication
    Low cost bumping by stencil printing. Process qualification for 200 mu m pitch
    ( 1998)
    Klöser, J.
    ;
    Heinricht, K.
    ;
    Jung, E.
    ;
    Lauter, L.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    A key issue for the introduction of flip chip technology for automotive, telecommunication and consumer applications is the implementation of low cost bumping processes, since the established methods need expensive equipment for metal sputtering and photolithography. At present, there are several methods for creating bumps on the die. One new method that has the potential to be much less expensive than current technologies is stencil printing. In this paper, the stencil printing method for wafer solder bumping is described using electroless nickel as a layer between the IC bond pad and the solder. Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost wafer bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) discussing quality and yield. A software tool for stencil layout design was developed and predicted bump heights are compared to experimental results. In the first part of the paper, the process flow of this economical bumping method for flip chip technology is described in detail. The key aspects of solder paste printing with optimized aperture size and shapes are outlined and the printing results are presented. In the second part of the paper, a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly are also shown.