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Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM
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Publication3D integration of image sensor SiP using TSV silicon interposer( 2009)
;Wolf, M.J. ;Zoschke, K. ;Klumpp, A. ;Wieland, R. ;Klein, M. ;Nebrich, L. ;Heinig, A. ;Limansyah, I. ;Weber, W. ;Ehrmann, O.Reichl, H.3D system integration is a fast growing field that encompasses different types of technologies. The technology chosen for a specific application will be selected according to the required electrical performance of the systems, the footprint, cost and time to market. Other important factors are the boundary conditions given for the specific components e.g. die size, integration compatibility, component availability (wafer vs. bare die) and testability. The paper discusses a specific 3D image sensor system for automotive applications. The system is based on wafer level technology using silicon interposer with through silicon vias (TSV's), a flip chip assembled sensor element and a microcontroller. The specific system concept, the technical solution and results are discussed. -
PublicationLow cost bumping by stencil printing. Process qualification for 200 mu m pitch( 1998)
;Klöser, J. ;Heinricht, K. ;Jung, E. ;Lauter, L. ;Ostmann, A. ;Aschenbrenner, R.Reichl, H.A key issue for the introduction of flip chip technology for automotive, telecommunication and consumer applications is the implementation of low cost bumping processes, since the established methods need expensive equipment for metal sputtering and photolithography. At present, there are several methods for creating bumps on the die. One new method that has the potential to be much less expensive than current technologies is stencil printing. In this paper, the stencil printing method for wafer solder bumping is described using electroless nickel as a layer between the IC bond pad and the solder. Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost wafer bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) discussing quality and yield. A software tool for stencil layout design was developed and predicted bump heights are compared to experimental results. In the first part of the paper, the process flow of this economical bumping method for flip chip technology is described in detail. The key aspects of solder paste printing with optimized aperture size and shapes are outlined and the printing results are presented. In the second part of the paper, a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly are also shown. -
PublicationThermo-mechanical reliability of flip chip structures used in DCA and CSP( 1998)
;Schubert, A. ;Dudek, R. ;Vogel, D. ;Michel, B.Reichl, H.The continuing demand towards high-density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology and chip size packages (CSP). The advantages in density, cost and electrical performance are obvious. Solder joints, the most widely used flip chip interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. This causes high thermally induced creep strain on the interconnects during temperature cycling and leads to early failure of the solder connections. The reliability of flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. However, over ranges of design, process, and material parameters, different failure modes are observed with significant dependence on material properties and geometry. Nonlinear finite element analysis for flip chip structures is carried out to investigate the reliability impact due to a number of selected design and material parameters. Especially two fundamental issues are addressed, namely, the optimization of thermomechanical properties of underfill materials and manufacturing process-induced defects. -
PublicationCharacterization of adhesive materials for high circuit density applications( 1998)
;Aschenbrenner, R. ;Mießner, R. ;Becker, K.-F.Reichl, H.This report presents the results of the evaluation of isotropic and anisotropic conductive adhesives for flip chip and chip size package applications. Samples consist of bumped testchips mounted on fine pitch rigid and flexible substrates. The finest pitch of the rigid glass substrates is 70 mu m and for the flexible substrates 100 mu m. Promising candidate for adhesive joining technique are the isotropic conductive adhesives. These adhesives are isotropic, which means that they conduct electricity equally in all directions. To use such adhesives in flip chip applications, the material has to be applied precisely onto the points to be connected, and is not allowed to flow and short circuit between circuit lines. The anisotropicaliy conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix at a concentration that is high enough to assure reliable conductivity between the substrate and the IC electrodes. The reliability evaluation was performed with special regard to the degradation and to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. A detailed thermo-mechanical analysis was used to determine the optimal cure schedule and to characterize the materials according to their physical properties. This kind of analysis method has also been used to optimize the curing profile, i.e. to shorten the curing time. -
PublicationImplementation of flip chip technology into volume manufacturing demonstration of processes( 1998)
;Jung, E. ;Heinricht, K. ;Kutzner, K. ;Klöser, J. ;Aschenbrenner, R. ;Reichl, H.Brommelhaus, A.Until now, use of flip chip technology has not been widespread in volume manufacturing, although it provides a number of significant advantages over standard surface mount devices. In particular, the cost aspect of using flip chip technology in a large scale manufacturing environment is expected to overcome the remaining issues. In order to illustrate the equipment and processes involved for incorporation of flip chip attachment into a production process, a demonstration center was established at FhG-IZM. Critical process steps were identified and addressed. This article gives a detailed insight into the actual implementation of a flip chip process into a SMD compatible production line, highlighting aspects of bump provision, cleaning, chip placement and underfilling. Bumping covers low cost processes such as electroless nickel as under-bump metallization (UBM) and stencil printed solder deposits using advanced printing technology. The necessity of cleaning and the key aspects for achievement of high reliability with industrial applied processes is highlighted. Required features of the placement machine and related critical issues are presented. Underfill application is also covered, focussing on important aspects for process optimization. -
PublicationReliability investigations of Sn/Pb and lead free solders for flip chip technology( 1998)
;Klöser, J. ;Jung, E. ;Heinricht, K. ;Kutzner, K. ;Ostmann, A.Reichl, H.This paper presents a flip chip technique based on electroless Ni-Au bumping and stencil printing of solder paste on wafers. The process steps and key aspects are described in detail. Experimental results for an ultra fine pitch printing technique on wafers are shown and reflowed solder bumps are characterized in terms of uniformity and strength. In comparison to eutectic SnPb solder, five alloys (BiSn, SnBiCu, SnAg, SnCu, AuSn) are investigated. In the second part of the paper, a comparison of solder alloy properties for applicability to flip chip technology, microstructure evaluation and phase compositions are presented. Microstructure coarsening and phase growth after thermal aging are also investigated. In order to assess the effect of substrate CTE on reliability, flip chip assembly was performed on LTTC and FR-4 substrates. Flip chip joint quality was investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, joint reliability results after thermal cycling with and without underfill on both substrate types are presented. -
PublicationReliability investigations for flip chip on flex using different solder materials( 1998)
;Kallmayer, C. ;Oppermann, H. ;Anhöck, S. ;Azadeh, R. ;Aschenbrenner, R.Reichl, H.Flip chip assembly on flexible organic substrates is facing increasing interest. In consumer products such as mobile phones or pagers, the assembly of the drivers of the LCD displays can be realized this way. Also there is a growing demand for Chip Size Packages (CSP). As a low cost version, CSPs based on flexible interposers have been developed. Especially for this application the reliability of the assemblies is important. Little is known about the aging behavior of these packages with different solder materials such as Pb-Sn and Au-Sn on standard tape metallizations as Cu-Au or Cu-Ni-Au. The impact of the bumping technology on the reliability is also a subject. Electroplated bumps are studied in comparison with meniscus bumps. Based on electroless Ni bumping, this cost effective technology is especially suited for flip chip on flex as the solder volume deposited is very small. In order to make useful predictions about the reliability of a metallurgical system it is necessary to understand the basic reactions involved. The scope of the investigations presented in this paper is to gain the data on interdiffusion in these systems, on the formation and growth of intermetallic phases. The impact of the presence of intermetallics and voids on the mechanical reliability is determined. The test program includes annealing of the flip chip assemblies at different temperatures and thermal cycling. Electrical measurements (Daisy chain) and shear tests are performed to determine the electrical and mechanical degradation of the solder joints. -
PublicationCorrelation of thermo-mechanical properties of adhesives with reliability of FC interconnections( 1998)
;Mießner, R. ;Aschenbrenner, R.Reichl, H.This paper presents an evaluation of isotropic and anisotropic conductive adhesives for flip chip applications. Samples consist of bumped test chips mounted on fine pitch rigid and flexible substrates. The finest pitches are 150 mu m for rigid FR4 substrates and 100 mu m for flex substrates. Isotropic conductive adhesives are promising candidates for adhesive joining. As they conduct electricity equally in all directions, the material must be applied precisely to the points to be connected, and not allowed to flow and short circuit between circuit lines. Anisotropic conductive adhesive materials are prepared by dispersing electrically conductive particles in an adhesive matrix. The concentration assures reliable conductivity between substrate and IC electrodes but insulation between adjacent bumps. Several adhesives, both commercial and experimental products, were investigated. A detailed thermo-mechanical analysis was used to characterize the materials according to their physical properties. This analysis method was also used to optimize the curing profile, i.e. to shorten curing time. The reliability evaluation was performed with special regard to the degradation and to interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity. Reliability test data was correlated with the thermo-mechanical properties. We thus derived simple criteria for adhesive selection for flip chip applications. -
PublicationQuality and yield of ultra fine pitch stencil printing for flip chip assembly( 1998)
;Heinricht, K. ;Klöser, J. ;Lauter, L. ;Ostmann, A. ;Reichl, H.Wolter, A.Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) with regard to quality and yield. A software tool for design of the stencil layout was developed and the predicted bump heights were compared to the experimental results. In the first part of the paper, a low cost bumping method for flip chip technology is described in detail. This technology is based on chemical Ni/Au deposition on wafers. For solder bumping on wafers, the key aspects of solder paste printing with optimized printable apertures are described and the printing results are presented. The second part of this paper is a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly. -
PublicationIntegration of flip chip assembly in the SMT process: manufacturing and productivity issues( 1998)
;Jung, E. ;Klöser, J. ;Heinricht, K. ;Lauter, L. ;Aschenbrenner, R.Reichl, H.Increasing interest in cost effective flip chip technologies leads to the development of various flexible methods for the deposition of solders and adhesives for use on chip or substrate. In this paper, the elements and basic process steps required for the development of a cost effective and flexible flip chip technology are described in detail. The deposition methods are focused on processes for stencil printing of solder paste on wafers and substrates. To achieve reproducible and homogeneous solder deposits, the process techniques for fine pitch printing require an improvement of the physical properties of the solder paste, of the stencil materials and stencil processing technologies, and of the printing equipment. Using solder pastes with very small particle sizes, a N2 atmosphere and a well controlled reflow furnace temperature profile is required. Apart from the technological aspects, the key point for the introduction of flip chip technology in a wide field of applications is the production equipment. The Fraunhofer Institute together with several industrial partners has set up a demonstration center for the assembly of flip chips (FC) and chip size packages (CSP). It is important to note that flip chip and CSPs can be used in conjunction with standard surface mount technology (SMT) devices. The development of these processes was performed by simultaneous engineering. In this paper, the experimental works are focused on the low cost bumping and assembly of flip chips and CSPs together with SMDs on different substrates.
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