Fraunhofer-Institut für Optronik, Systemtechnik und Bildauswertung IOSB

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  • Publication
    Analysis of industrial production environments and derivation of a novel channel model towards optical wireless communication
    ( 2018)
    Schneider, Daniel
    ;
    Flatt, Holger
    ;
    Jasperneite, Jürgen
    ;
    Stübbe, Oliver
    Today radio based wireless communication technologies offer limited performance, whereas optical wireless com- munication systems (OWC) propose potentially a high performant, scalable communication system conforming to real time conditions. However, current studies imply, that OWCs still lack the necessary performance and robustness level for most wireless applications in industrial production environments. In this approach several types of noises for free-space optical communication systems are empirically analysed in an accredited, exemplary industrial production environment. While the channel noise is usually modelled by the signal to noise ratio it is found that real environments cannot be approximated by the usual static additive white gaussian noise. In this approach the accumulated measurement data represents the spectrum variation of different locations and times relating to different types of noise sources. The implementation in a total channel model allows the optimization of OWC designs like the channel access scheme or the modulation type concerning performance and robustness. Furthermore an additional measurement setup is proposed, capable of measuring and classifying existing noise sources in order to serve the design of OWC systems in industrial production environments.
  • Publication
    Entwurf eines Kanalmodells für Visible Light Communication in dynamischen, industriellen Umgebungen
    ( 2017)
    Schneider, Daniel
    ;
    Flatt, Holger
    ;
    Jasperneite, Jürgen
    ;
    Stübbe, Oliver
    In diesem Beitrag werden die Störeinflüsse für optische Freiraumkommunikation in industriellen Produktionsumgebungen empirisch analysiert und ein Modellierungsansatz abgeleitet. Um drahtlose Kommunikationstechnologien einzusetzen, sind erhebliche Resistenzen gegenüber Störeinflüssen erforderlich, die Visible Light Communication (VLC) bis heute nicht vollständig erfüllt. Anhand von empirischen Messreihen wird in diesem Beitrag nachgewiesen, dass bei der Systemauslegung von VLC, anders als bisher, unterschiedliche Störquellen zu berücksichtigen sind, die orts- und zeitvariante Eigenschaften haben. Auf empirischen Untersuchungen basierend, wird eine alternative Berechnung der gesamten Störquellenleistung vorgeschlagen, die unmittelbar Auswirkung auf das Signal-Rausch-Verhältnis (SNR) und die maximal verfügbare Kanalkapazität hat. Der vorgestellte Ansatz dient dazu VLC-Systeme auch für industrielle Produktionsumgebungen auslegen zu können.
  • Publication
    Modellbasierter Entwurfsassistent zur Auslegung spezifischer Architektur- und Konfigurationseigenschaften von Kommunikationsnetzen mit Echtzeitanforderungen
    ( 2016)
    Leßmann, Gunnar
    ;
    Schneider, Daniel
    ;
    Flatt, Holger
    ;
    Schriegel, Sebastian
    ;
    Jasperneite, Jürgen
    Industrielle Netzwerke werden immer komplexer durch den Einsatz neuer Technologien wie Time Sensitive Networking (TSN). Die Anforderungen werden zudem verschärft durch sich ändernde gesetzliche Vorgaben wie z.B. bei Smart Grids. Planer solcher Netzwerke haben häufig spezifische Echtzeitanforderungen, Datenraten und Redundanzanforderungen zu beachten, deren Realisierung u.a. abhängig sind von der Leistungsfähigkeit und der Topologie des Netzwerkes. Designalternativen sollten daher quantitativ bewertbar sein, um individuelle Planungsaspekte erweiterbar sein und eine generelle Anwendbarkeit aufweisen. Da diese Kriterien aktuell von keinem verfügbaren Planungswerkzeug erfüllt werden, wurde in diesem Beitrag mit Hilfe von Matlab Simulink® ein generisches und skalierbares Modell von Netzwerkkomponenten erstellt. Diese Komponenten können parametriert und in einer anwendungsnahen Topologie kombiniert werden. Leistungsqualifizierende Parameter wie die Echtzeitfähigkeit, Auslastung der Komponenten, Ausfallsicherheit und die Topologie wurden zur Bewertung von Designszenarien eines beispielhaften Windparks herangezogen. Eine Erweiterung des Modells ermöglicht es darüberhinausgehend die Auswirkungen von zukünftigen Technologien, wie z.B. TSN zu analysieren.
  • Publication
    Automatic determination of synchronization path quality using PTP bridges with integrated inaccuracy estimation for system configuration and monitoring
    ( 2015)
    Schriegel, Sebastian
    ;
    Biendarra, Alexander
    ;
    Ronen, Opher
    ;
    Flatt, Holger
    ;
    Leßmann, Gunnar
    ;
    Jasperneite, Jürgen
    Many network applications like motion control or precise monitoring of machines need precise knowledge about the time synchronization accuracy. But time synchronization accuracy depends on the performance of PTP nodes, network topology, environmental conditions and various other factors. This makes the determination of synchronization accuracy a complex task. A mechanism for determining the worst case synchronization accuracy is defined in the PTP Power Profile. A TLV is used for accumulating a vendor defined worst case inaccuracy. However in practice when using this approach the inaccuracy values are often much higher than the real synchronization accuracy. In this paper, a technique for automatic determination of synchronization path quality is investigated. It utilizes PTP Bridges with an inaccuracy estimation performed using an inaccuracy model that is separated into static and dynamic inaccuracy contributors. One assumption is that the inaccuracy in the PTP time observed by a bridge, depends on the position of the bridge in the sync path. The latter is due to accumulation of more, possibly independent, random contributors. The effect of increasing deviation is modeled and verified using an experimental setup. The paper concludes that detailed knowledge about the PTP network (cable lengths, inaccuracy contribution metrics for the specific nodes within the sync path, etc.) are useful for automatic determination of the synchronization path quality, synchronization monitoring, system configuration and diagnosis. We suggest an enhancement to the TimeInaccuracy TLV that may possibly be incorporated within the next PTP revision, to better facilitate the protocol support for the above functions.
  • Publication
    An architectural approach for reconfigurable industrial I/O devices
    ( 2014)
    Kirschberger, Daniel
    ;
    Flatt, Holger
    ;
    Jasperneite, Jürgen
    This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern FPGAs is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.
  • Publication
    An OPC UA based approach for dynamic-configuration of security credentials and integrating a vendor independent digital product memory
    ( 2014)
    Blume, Marco
    ;
    Koch, Nils
    ;
    Imtiaz, Jahanzaib
    ;
    Flatt, Holger
    ;
    Jasperneite, Jürgen
    ;
    Schleipen, Miriam
    ;
    Sauer, Olaf
    ;
    Dosch, Steffen
    This paper presents an approach to securely integrate industrial devices into automation systems with a minimal engineering effort. A special specific focus is on the needed communication architecture that is based on the platform independent and vendor neutral technology OPC UA. The paper also describes the need of a digital product memory besides a life cycle data harvesting to facilitate such seamless integration; this is by means of presenting semantics of operations to an external system. As part of the work, a case study has been identified; different architectural aspects are evaluated and essential system components are realized/implemented/integrated as a proof of concept. Principle results include the implementation of a BeagleBone Black-based Secure Plug & Work I/O field device with an extended real-time industrial communication interface and a semantically enriched OPC UA server that provides vendor neutral configuration and an I/O data service interface. Furthermore, the result provides a platform independent and standardized way to represent a field device to external systems, to enable intelligent technical systems to communicate and orchestrate a seamless and secure integration.
  • Publication
    Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture
    ( 2013)
    Flatt, Holger
    ;
    Jasperneite, Jürgen
    ;
    Dennstedt, Daniel
    ;
    Tran, Dinh Hung
    This paper presents the mapping of the seamless redundancy protocols PRP and HSR in combination with IEEE 1588 based clock synchronization onto a configurable CPU/FPGA based Redundancy Box architecture. Whereas core functions of PRP, HSR, and IEEE 1588 are mapped onto the FPGA, a CPU executes the control parts of these protocols. An optional attached standard switch ASIC provides direct connection to several network devices. For validation purpose, a special embedded platform is proposed that is composed of an FPGA and a commercial off-the-shelf switch ASIC. The results show that even a low-cost Altera Cyclone IV FPGA comprising 74,000 logic elements fulfills the requirements for protocol processing at 100 Mbps per port. Minimum size frames are forwarded by the FPGA up to two times faster than competitive implementations. Three connected PRP/HSR RedBoxes and an IEEE 1588 clock master are synchronizing in laboratory within an accuracy of 30 ns. Using several RedBoxes in PRP and HSR mode, a seamless redundancy is demonstrated for a PROFINET RT test network and supplemental network components. Overall, the presented RedBox can be flexibly integrated into time-synchronized industrial networks in order to significantly increase the communication reliability.
  • Publication
    Ein FPGA-Ansatz zur Anwendung von PRP/HSR-Redundanzprotokollen mit IEEE 1588 Zeitsynchronisation in der Automatisierungstechnik
    ( 2013)
    Flatt, Holger
    ;
    Jasperneite, Jürgen
    ;
    Rachfuß, Joachim
    Dieser Beitrag präsentiert die Abbildung der stoßfreien Redundanzprotokolle PRP und HSR in Kombination mit IEEE 1588 basierter Zeitsynchronisation auf eine konfigurierbare CPU/FPGA-basierte RedBox-Architektur. Kernfunktionen der Protokolle PRP, HSR und IEEE 1588 werden dabei auf das FPGA abgebildet. Eine CPU setzt die Steuerungsaufgaben des Protokolls um. Ein optionaler Standard-Switch-ASIC stellt eine direkte Kommunikation zu mehreren Netzwerkgeräten her. Für Testzwecke wird eine spezielle eingebettete Plattform vorgeschlagen, welche aus einem FPGA und einem kommerziell verfügbarem Switch-ASIC besteht. Die Ergebnisse zeigen, dass ein kostengünstiges Altera Cyclone IV FPGA mit 74.000 Logikelementen die Anforderungen für eine Protokollverarbeitung bei 100 MBit/s pro Port erfüllt. Frames minimaler Größe werden vom FPGA zweimal schneller weitergeleitet als bei anderen Implementierungen. Drei verbundene PRP/HSR-RedBoxen und ein IEEE 1588 Clock-Master synchronisieren sich unter Laborbedingungen mit einer Genauigkeit von 30 ns. Somit kann die RedBox flexibel in zeitsynchronisierte industrielle Netzwerke integriert werden, um die Zuverlässigkeit der Kommunikation signifikant zu erhöhen.
  • Publication
    An FPGA based HSR architecture for seamless PROFINET redundancy
    ( 2012)
    Flatt, Holger
    ;
    Schriegel, Sebastian
    ;
    Neugarth, Thimo
    ;
    Jasperneite, Jürgen
    This paper presents the mapping of the High-Availability Seamless Redundancy (HSR) protocol to PROFINET RT. Whereas common PROFINET RT components that implement the Media Redundancy Protocol (MRP) are requiring up to 200 ms for recovery after link failures, HSR provides seamless redundancy. In order to overcome the incompatibilities between PROFINET and HSR a configurable HSR RedBox is implemented. The hardware architecture, running at 100 MHz, is mapped onto an Altera Stratix IV FPGA and is capable of processing up to 100 Mbps per port. Using several RedBoxes in a ring, a seamless redundancy is demonstrated for a PROFINET RT test network, using 1 ms cycle time with 3 ms watchdog. The presented architecture is highly configurable and can be mapped both to high-end and low-end FPGAs and therefore fulfills industrial requirements.
  • Publication
    An FPGA based approach for the enhancement of COTS switch ASICs with real-time Ethernet functions
    ( 2012)
    Flatt, Holger
    ;
    Schriegel, Sebastian
    ;
    Jasperneite, Jürgen
    ;
    Schewe, F.
    This paper presents an approach for the enhancement of standard switch ASICs with real-time Ethernet functions. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non real-time frames, an attached FPGA implements cut-through switching of real-time frames. The proposed FPGA architecture supports configuration of port numbers, bandwidth reservation for real-time frames and utilizes flow-control mechanisms of the ASIC in order to keep frame buffer sizes low. Mapping exemplary RTE extensions of PROFINET IRT onto a Xilinx Spartan 6 FPGA demonstrates the capability of providing band-width reservation and cut-throughforwarding of real-time frames. Therefore, the approach benefits from the innovations made by the switch manufacturers, whereas only a small amount of functions has to be mapped onto an FPGA.