Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE
    ( 2022)
    Mackowiak, Piotr
    ;
    Erbacher, Kolja
    ;
    Schiffer, Michael
    ;
    Manier, Charles-Alix
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    Töpper, Michael
    ;
    Ngo, H.-D.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    This article presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched micro electromechanical system (MEMS) SiC Device. By optimizing the process, etch depth of 200 μm with an etch rate of up to 2 μm /min can be achieved for via etching. In addition, a design of experiments (DoEs) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the SiC. Hereby, vertical sidewalls with low micromasking, low microtrenching and an etch rate of up to 4 μm /min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200- μm -thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50- μm thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments MEMSs and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3-D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.
  • Publication
    A Novel Quantitative Adhesion Measurement Method for Thin Polymer and Metal Layers for Microelectronic Applications
    ( 2022)
    Woehrmann, Markus
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    Mackowiak, Piotr
    ;
    Schiffer, Michael
    ;
    Lang, K.-D.
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    Schneider-Ramelow, M.
    Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface's fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.
  • Publication
    Design and modeling of a novel piezoresistive microphone for aero acoustic measurements in laminar boundary layers using FEM and LEM
    ( 2021)
    Erbacher, Kolja
    ;
    Ngo, Ha-Duong
    ;
    Mackowiak, Piotr
    ;
    Wu, Lixiang
    ;
    Julliard, Emmanuel
    ;
    Spehr, Carsten
    In this paper the modeling and simulation results of a piezo-resistive microphone are presented and a possible fabrication process flow and characterization concept of the sensor are described. The main objective in this funded AEROMIC project is to develop a thin and small in size microphone, which can be integrated into a flexible array, that can be mounted onto an airplane hull for flight tests. The microphone array should be no thicker than 2 mm and should contain more than 80 flush mounted single microphones, allowing acoustic measurement without disturbance of the laminar boundary layer. The pitch of the microphone sensors in the array enable high spatial resolution of the pressure fluctuation. The optimization of geometry of single sensor microphone has been done using FEA (Finite Element Analysis). For the optimization of the geometry of the single microphone chip, FEA of the air damped dynamic behavior of the diaphragm is modeled in Ansys Harmonic Response Analyses with Acoustics ACT package. To model the array on system level, a lumped-element model (LEM) is set up to predict spatial resolution and signal to noise ratio. Derived from the FEA results, a sensor chip layout with three membrane sizes is presented.