Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    A novel hermetic encapsulation approach for the protection of electronics in harsh environments
    ( 2022-11-11)
    Spanier, Malte
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    Pawlikowski, Jakub
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    Ziesche, Steffen
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    Kappert, Holger
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    Ostmann, Andreas
    ;
    Jägle, Martin
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    Schneider-Ramelow, Martin
    Technologies and building blocks for the realization of reliable electronic systems for the use in harsh environments are attracting increasing intention. Harsh environments are for instance high temperature, pressure, mechanical stress and/or submerge into corrosive liquids, or the combination thereof. In the first place electronic components like integrated circuits or passive components which constitute the electronic system need to be operational under harsh conditions. On system level also the interconnections and package materials need to withstand the loading conditions. Printed circuit board embedding technology is a highly promising approach to realize this kind of electronic systems. Embedded semiconductors and passive components are mechanically protected from the environmental stresses by the epoxy/glass fibre compound into which they are encapsulated. Furthermore, novel types of high temperature laminate materials are commercially available since a few years. In an electroless plating process a fully hermetic metallic encapsulation can be added to the modules. This encapsulation acts as a protective barrier when they are immersed into corrosive liquids or gases. The external electrical connections out of the package are realized by ceramics with metallic feed throughs. They are assembled onto the modules (prior to the metallic encapsulation) using sinter-lamination-technology, i.e. the simultaneous build-up lamination and a sintering process. Two application demonstrators were realized in order to show the general viability of the encapsulation process. All used materials are commercially available. Industrial process equipment was used throughout the manufacturing. Subsequent reliability tests provide evidence for the general robustness and functionality of the modules under harsh environmental conditions. This work was part of the Fraunhofer lighthouse project “eHarsh” which was funded by the Fraunhofer Society.
  • Publication
    Low-loss optical single-mode waveguide platform in thin glass with wide spectral range
    ( 2022)
    Schröder, Henning
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    Schwietering, J.
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    Kirsch, Oliver
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    Wachholz, Philipp
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    Lewoczko-Adamczyk, Wojciech
    Current developments are pushing the integration of optical technologies deeper into the architecture of data centers,1 a trend in which co-packaging figures prominently due to its many inherent advantages2, 3. Several materials are used as a basis for these co-packaged platforms, but glass stands out for its many positive properties, such as high thermal and dimensional stability, great optical transparency, excellent high-frequency properties for electric circuits, and extremely low cost. To seize these advantages, we pursued an approach called electro-optical circuit board (EOCB), in which optical and electrical interconnections are realized by glass-integrated optical waveguides and electrical circuits on both sides of the glass board. An ion-exchange technique was developed to integrate low-loss optical single-mode waveguides into large-sized glass boards (457 mm x 303 mm). In the reported work, the next milestone in developing this process was achieved by reducing the diffusion metal mask opening's width from 6 μm to 3 μm by mask-less laser patterning. These smaller mask opening allow for optical waveguides with a more circular modal field shape resulting in smaller coupling losses to optical fibers. Additionally, the reduction of propagation losses of multi-mode waveguides for wavelengths down to the visible range was achieved. This opens up the field of sensing and quantum application to EOCBs.
  • Publication
    Sub-TeraHertz Modular Array Layout Optimization under Fabrication Constraints
    ( 2022)
    Dehkordi, S.K.
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    Schwanitz, Oliver
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    Marandi, M.K.
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    Kaiser, Michael
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    Le, Thi Huyen
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    Ndip, Ivan
    ;
    Caire, G.
    Millimeter wave (mmWave) and sub-TeraHertz (sub-THz) multi-user multiple-input multiple-output (MUMIMO) communications operating in the frequency spectrum (30-300 GHz) have already been identified as the most promising candidate for the second phase of 5G and Beyond (5GB) wireless systems aiming to achieve broadband data communications at rates higher than 1 Gb/s while operating in very dense urban small-cell environments. Due to the presence of strong isotropic pathloss in mmWave/sub-THz frequencies, high antenna gains realized through large antenna arrays will be required to mitigate these effects. The small wavelengths under which mmWave and s-THz systems operate, allow for integration of more compact antenna elements. However, the fabrication of such antennas poses challenges such as positioning tolerance. In this work, we introduce a novel modular array synthesis approach and further investigate the effect of non-ideal element/module positions within an array and provide an optimization framework to minimize the expected synthesized array pattern error taking positioning tolerances into account. Furthermore, we use the realized element pattern of the proposed D-Band patch element with an RF bandwidth of over 10 GHz to demonstrate the results of the proposed optimization algorithm.
  • Publication
    Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE
    ( 2022)
    Mackowiak, Piotr
    ;
    Erbacher, Kolja
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    Schiffer, Michael
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    Manier, Charles-Alix
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    Töpper, Michael
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    Ngo, H.-D.
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    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    This article presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched micro electromechanical system (MEMS) SiC Device. By optimizing the process, etch depth of 200 μm with an etch rate of up to 2 μm /min can be achieved for via etching. In addition, a design of experiments (DoEs) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the SiC. Hereby, vertical sidewalls with low micromasking, low microtrenching and an etch rate of up to 4 μm /min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200- μm -thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50- μm thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments MEMSs and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3-D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.
  • Publication
    Dry etch processing in fan-out panel-level packaging - An application for high-density vertical interconnects and beyond
    ( 2022)
    Schein, F.-L.
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    Voigt, C.
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    Gerhold, L.
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    Tsigaras, I.
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    Elghazzali, M.
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    Sawamoto, H.
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    Strolz, E.
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    Rettenmeier, R.
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    Kahle, Ruben
    ;
    Böttcher, Lars
    In this work, we demonstrate advances in plasma dry etch technology applied to common materials in semi-additive fineline processing for panel-level packaging. Emphasis is placed on deep reactive-ion etching into organic dielectric build-up materials as a scalable process for making vertical interconnects (vias). A capacitively coupled dual frequency plasma module was used for our experiments. We investigate the influence of different process parameters and gas mixtures on via shape, via sidewall quality and residue formation. To enable material-selective etching, a metallic hard mask is used, patterned by direct imaging lithography. For the removal of the hard mask we introduce a non-etching lift-off approach. Furthermore, a dry etch removal of sputtered Ti barrier and Cu seed layers is shown.
  • Publication
    High-k dielectric screen-printed inks for mechanical energy harvesting devices
    ( 2022)
    Leese, H.S.
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    Tejkl, M.
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    Vilar, L.
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    Georgi, L.
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    Yau, H.C.
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    Rubio, N.
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    Reixach, E.
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    Buk, J.
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    Jiang, Q.
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    Bismarck, A.
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    Hahn, Robert
    ;
    Shaffer, M.S.P.
    There are a range of promising applications for devices that can convert mechanical energy from their local environment into useful electrical energy. Here, mechanical energy harvesting devices have been developed to scavenge low-frequency energy from regular biomotion such as joint movement and heel strike. Specifically, these harvesters exploit novel printed nanocomposite dielectric inks in combination with commercially available conductive elastomers to develop a low cost, high performance embodiment of a variable capacitance mechanism device. The filler of the nanocomposite dielectric ink, consists of high-k dielectric nanoparticles (barium titanate and strontium doped barium titanate) functionalised with poly(methyl methacrylate) to improve the interface with the epoxy matrix. Characterisation by thermogravimetric analysis coupled to mass spectrometry and X-ray photoelectron spectroscopy confirmed the successful covalent grafting of up to ca. 16 wt% poly(methyl methacrylate) onto the dielectric nanoparticle surfaces, with a thickness of approximately 14 nm, measured by transmission electron microscopy. The dielectric inks were screen printed onto copper-polyimide foils, resulting in large area and flexible five to twenty-micron thick films with dielectric constants up to 45. Nanoparticle polymer functionalisation improved the homogeneity and stability of the inks. Using these screen-printed dielectrics with the commercial conductive elastomer, the mechanical energy harvester prototype demonstrated high mechanical cycling stability and low leakage current. It provided a promising power density of 160 μW cm-3, at low frequency (0.5 Hz), over a 1000 cycles, making the device suitable for wearable applications. This type of harvester has two advantages over the state of the art: it is mechanically flexible for integration into wearables and can be produced at low cost with printing methods. This journal is
  • Publication
    A Novel Quantitative Adhesion Measurement Method for Thin Polymer and Metal Layers for Microelectronic Applications
    ( 2022)
    Woehrmann, Markus
    ;
    Mackowiak, Piotr
    ;
    Schiffer, Michael
    ;
    Lang, K.-D.
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    Schneider-Ramelow, M.
    Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface's fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.
  • Publication
    Design Tool for Temperature Estimation on PCB
    ( 2022)
    Schroeder, Bernd
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    Hoffmann, Stefan
    ;
    Mueller, Olaf
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    Stube, Bernd
    ;
    Hoene, Eckart
    The paper presents a novel thermal analysis approach based on an estimation of current density, power dissipation and temperature distribution of a printed circuit board. The implemented algorithms are integrated in a design tool that can be used as an add-on tool via interfaces to commercial EDA tools. The calculations are based on imported layout data from the EDA tools and not on Gerber data. The current density is calculated with a separate PEEC solver. The developed design tool automatically generates the necessary 3D model, activates the PEEC solver and extracts its calculation results. Subsequently, the implemented thermal solver of the design tool calculates the power dissipation and temperature distribution for a previously assigned current. This efficiently supports the PCB designer already during the layout process. The method is validated by simulations and measurements on typical boards.
  • Publication
    Experimental and simulative study of warpage behavior for fan-out wafer-level packaging
    ( 2022)
    Dijk, Marius van
    ;
    Huber, Saskia
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    Stegmaier, Andreas
    ;
    Walter, Hans
    ;
    Wittler, Olaf
    ;
    Schneider-Ramelow, M.
    Controlling warpage effects in fan-outwafer-level packaging (FO-WLP) is of key importance for realizing reliable and cost-efficient system in packages (SiPs). However, warpage effects can occur during the manufacturing process, caused by a combination of different processing temperatures, different materials, and the changing properties of the materials (e.g. polymerization and related cure shrinkage). One approach to controlling warpage could be realized by assessing a numerical simulation workflow of the FO-WLP process chain, in which the relevant material properties and geometry are used as input. Since there are many different steps included in the FO-WLP process, accompanied by complex material behavior, this workflow is not straight-forward. In the present paper, the first FO-WLP processing steps are investigated in detail by performing extensive thermo-mechanical material characterization, temperature-dependent warpage measurements, and numerical simulations. The investigation focuses on two epoxy mold compound (EMC) materials with completely different physical properties. The warpage measurements of bi-material (EMC and silicon) samples reveal an irreversible effect after passing certain processing temperatures, which are significant for final warpage at room temperature. A new approach to measuring the coefficient of thermal expansion (CTE) is discussed, using a temperature profile based on the temperature in the process, instead of the three identical temperature ramps suggested by the typical standards. This new approach makes it possible to determine possible shrinkage effects. Within the simulation model, the hysteresis effect observed in the experiment is taken into account by adding a shrinkage strain as well as changing the CTE values during the process. A very good agreement between the experiment and simulation is achieved, which is shown for several demonstrators with different epoxy mold compound materials and thicknesses.
  • Publication
    Low-Temperature Processible Highly Conducting Pastes for Printed Electronics Applications
    ( 2022)
    Scenev, V.
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    Szalapak, J.
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    Werft, Lukas
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    Hoelck, Ole
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    Jakubowska, M.
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    Krshiwoblozki, Malte von
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    Kallmayer, Christine
    ;
    Schneider-Ramelow, M.
    Scalable additive manufacturing of printed electronics is a growing field accompanied by increasing demands for reliable and integrable functional flexible printed electronic devices. Herein, a novel type of electrically conducting silver-based pastes for additive manufacturing is demonstrated. These pastes are designed for stencil- and screen-printing and can be post-processed at very low temperatures, at ambient. Furthermore, printed lines made with the pastes exhibit an electrical sheet resistance below 60 mΩ sq-1 even after room temperature and only 25 mΩ sq-1 after two minutes of curing at 90 °C.