Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Patent
    Verfahren zur Verbindung eines flexiblen Substrats mit einem Chip
    ( 2004)
    Azdasht, G.
    ;
    Zakel, E.
    ;
    Reichl, H.
    Process for the thermal binding of contact elements (14, 15) of a flexible substrate (10) with contact metallizations (17) of an electronic component (12), whereby the flexible substrate has a substrate (13) made of plastic and the contact elements are applied with energy from their rear, i.e. in the form of a laser beam (11), whereby the transparency of the substrate (19), the absorption of the contact elements (14, 15) and the wavelength of the laser beam (11) are matched so that the laser beam is guided mainly through the substrate (13) and is absorbed in the contact elements (14, 15), and the substrate (10) is applied with pressure in such a way that the contact elements (14, 15) of the substrate (10) and the contact metallizations (17) of the component (12) are in contact with each other when the laser beam (11) is applied to them.
  • Patent
    Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
    ( 2002)
    Oppermann, H.H.
    ;
    Zakel, E.
    ;
    Azdasht, G.
    ;
    Kasulke, P.
    The chip module (20) has at least one chip (22) attached to a chip carrier (21) provided by a foil and a plastics carrier layer (23), providing a conductor path structure (24) with conductor paths (28) connected to corresponding contact pads (32) of the chip on the front side and provided with external contact regions (26) on the rear side, for connection to a circuit board substrate (31). The external contact regions are provided by openings in the carrier layer of the chip carrier at the rear side of the conductor paths, aligned with terminal pads (30) for the chip provided by the circuit board substrate. USE - For chip-scale package. ADVANTAGE - Simple manufacture of chip module with reduced number of individual steps.
  • Patent
    Verfahren zum Bilden einer strukturierten Metallisierung auf einem Halbleiterwafer
    ( 2002)
    Aschenbrenner, R.
    ;
    Azdasht, G.
    ;
    Zakel, E.
    ;
    Ostmann, A.
    ;
    Motulla, G.
    A process for forming a structured metallisation on a semiconductor wafer (20), in which a passivation layer (22) is applied onto the wafer main surface and is structured to define a bond pad (24), involves (a) producing a metal bump on the bond pad (24); (b) producing an activated dielectric on the passivation layer regions on which the structured metallisation is to be formed; and (c) chemically depositing metal on the activated dielectric and the metal bump. Also claimed are alternative processes involving (i) carrying out step (b), activating the bond pad and chemically depositing metal on the activated regions and the activated bond pad; (ii) producing an activated electrically conductive paste (40) on the bond pad (24) and on the passivation layer regions on which the structured metallisation is to be formed, followed by chemical metal deposition on the paste (40); or (iii) carrying out step (a), producing a structured metal foil on the metal bump and on the passivation layer reg ions on which the structured metallisation is to be formed, followed by chemical metal deposition on the metal foil. USE - Especially for chip wiring production on a semiconductor wafer. ADVANTAGE - Wiring of chip edge pads of the wafer in a planar configuration can be carried out in a simpler, quicker and less expensive manner than conventional processes which employ expensive sputtering operations.
  • Patent
    Verbindungsstruktur
    ( 2002)
    Azdasht, G.
    ;
    Kasulke, P.
    ;
    Badrihafifekr, H.
    ;
    Weiss, S.
    ;
    Zakel, E.
    The components are of materials of different expansion coeffts., and at least one component is an electric power element. High melting material are used for connection structure, forming individual connection elements (29) between the contact faces (27,28) of the component elements (21,22). Preferably each connection element is made of a single material and directly coupled to the contact faces. Typically as a laminated structure. The connection elements may contain an intermediate layer of a soldering material for contacting the opposite contact faces. USE/ADVANTAGE - For electronic power elements, such as laser diodes etc. Reliable reduction of thermally induced stresses without impairing the component service life.
  • Patent
    Verfahren zur Ausbildung einer raeumlichen Chipanordnung und raeumliche Chipanordung
    ( 1998)
    Oppermann, H.H.
    ;
    Azdasht, G.
    ;
    Kasulke, P.
    ;
    Zakel, E.
  • Patent
    Verfahren zur Formung von Anschlusshoeckern auf elektrisch leitenden mikroelektronischen Verbindungselementen zum lothoecker-freien Tab-Bonden
    ( 1997)
    Azdasht, G.
    ;
    Zakel, E.
    ;
    Beutler, U.
    The invention describes a process for the shaping of electrically conducting terminal bumps on electrically conducting microelectronic connecting elements. In conventional processes, a terminal bump is produced in a deep-draw process, whereby the connecting element is pressed by a die into a recess of a substrate on which the connecting element is fixed. The disadvantage is that a recess occurs next to the terminal bump on the side facing the die, said recess being deleterious for the mechanical loading capability and also for subsequent tab bonding. In the process according to the invention, however, a shaping tool is pressed onto part of the surface of a connecting element, whereby one or more terminal bumps are formed by the plastic deformation of the connecting element material in this part of the surface due to the geometry of the shaping tool, however, the connecting element suffers no further deformation outside said part of the surface. The advantages of the process according t o the invention are that no shaping substrate matched to the desired terminal bumps is required, that conventional wire bonding units can be used, that the process is fast, low-priced and precise and that the mechanical loading capability of a connecting element, in particular a metal lead, is .. due to the formation ..
  • Patent
    Chip-Gehaeusung sowie Verfahren zur Herstellung einer Chip-Gehaeusung
    ( 1996)
    Azdasht, G.
    ;
    Zakel, E.
    ;
    Reichl, H.
    Housing to receive at least one electronic component, such as a chip (11) or similar, and process for the production of this type of housing having a capping layer (12) and a counter capping layer (13) which receive the electronic component between each other, whereby the capping layer (12) and the counter capping layer (13) are provided with conductors (15, 16 and 24, 25) on their inner sides in such a way that the conductors (15, 16) of the capping layer (12) connect terminal areas (21, 22) of the component (11) with the conductors (24, 25) of the counter capping layer (13) and the conductors (24, 25) of the counter capping layer (13) end in terminal areas (32, 33) of the housing (10), whereby the capping layer (12) and/or the counter capping layer (13) has/have a flexible substrate (14) and are interconnected in the capping layer connection areas (73) surrounding the component (11).