Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Patent
    Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
    ( 2002)
    Oppermann, H.H.
    ;
    Zakel, E.
    ;
    Azdasht, G.
    ;
    Kasulke, P.
    The chip module (20) has at least one chip (22) attached to a chip carrier (21) provided by a foil and a plastics carrier layer (23), providing a conductor path structure (24) with conductor paths (28) connected to corresponding contact pads (32) of the chip on the front side and provided with external contact regions (26) on the rear side, for connection to a circuit board substrate (31). The external contact regions are provided by openings in the carrier layer of the chip carrier at the rear side of the conductor paths, aligned with terminal pads (30) for the chip provided by the circuit board substrate. USE - For chip-scale package. ADVANTAGE - Simple manufacture of chip module with reduced number of individual steps.
  • Patent
    Verbindungsstruktur
    ( 2002)
    Azdasht, G.
    ;
    Kasulke, P.
    ;
    Badrihafifekr, H.
    ;
    Weiss, S.
    ;
    Zakel, E.
    The components are of materials of different expansion coeffts., and at least one component is an electric power element. High melting material are used for connection structure, forming individual connection elements (29) between the contact faces (27,28) of the component elements (21,22). Preferably each connection element is made of a single material and directly coupled to the contact faces. Typically as a laminated structure. The connection elements may contain an intermediate layer of a soldering material for contacting the opposite contact faces. USE/ADVANTAGE - For electronic power elements, such as laser diodes etc. Reliable reduction of thermally induced stresses without impairing the component service life.
  • Patent
    Verfahren zum Anbringen eines Bauelements an einem plattenfoermigen Traeger
    ( 1998)
    Azdasht, G.
    ;
    Kasulke, P.
    The component mounting method is used for attaching an electronic component (10) to the surface of a carrier plate (12,18), with a solder layer inserted between the component and the carrier plate surface. An optical fibre or optical fibre bundle is applied to the opposite side of the carrier plate and supplied with a laser light pulse provided for melting the solder layer, to provide a mechanical and electrical connection between the component and the carrier plate. USE - For attaching laser diode to Cu coated circuit board. ADVANTAGE - Reduced thermic loading of electronic component.
  • Patent
    Verfahren zur Ausbildung einer raeumlichen Chipanordnung und raeumliche Chipanordung
    ( 1998)
    Oppermann, H.H.
    ;
    Azdasht, G.
    ;
    Kasulke, P.
    ;
    Zakel, E.
  • Patent
    Verfahren zur Herstellung einer Durchkontaktierung sowie Chiptraeger und Chiptraegeranordnung mit einer Durchkontaktierung
    ( 1997)
    Azdasht, G.
    ;
    Kloeser, J.
    ;
    Kasulke, P.
    The method involves providing a deformable substrate (11) and using a form tool (15). The substrate has a polyimide film (12) sandwiched between two metallised layers (13,14), e.g. of copper. During production, the metallisation layers are simultaneously pressed by displacement of the substrate. The substrate is displaced in a process involving pressure and temperature using the form tool and e.g. application of e.g. current, laser radiation, or ultrasound, the through contact is formed. USE/ADVANTAGE - For multi-layer technology, multi-grid array, and ball-grid array. Permits cheap formation of through-contact with substrate. Provides chip carrier arrangement using substrate preparation with reduced expenditure.