Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    A novel hermetic encapsulation approach for the protection of electronics in harsh environments
    ( 2022-11-11)
    Spanier, Malte
    ;
    Pawlikowski, Jakub
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    Ziesche, Steffen
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    Kappert, Holger
    ;
    Ostmann, Andreas
    ;
    Jägle, Martin
    ;
    Schneider-Ramelow, Martin
    Technologies and building blocks for the realization of reliable electronic systems for the use in harsh environments are attracting increasing intention. Harsh environments are for instance high temperature, pressure, mechanical stress and/or submerge into corrosive liquids, or the combination thereof. In the first place electronic components like integrated circuits or passive components which constitute the electronic system need to be operational under harsh conditions. On system level also the interconnections and package materials need to withstand the loading conditions. Printed circuit board embedding technology is a highly promising approach to realize this kind of electronic systems. Embedded semiconductors and passive components are mechanically protected from the environmental stresses by the epoxy/glass fibre compound into which they are encapsulated. Furthermore, novel types of high temperature laminate materials are commercially available since a few years. In an electroless plating process a fully hermetic metallic encapsulation can be added to the modules. This encapsulation acts as a protective barrier when they are immersed into corrosive liquids or gases. The external electrical connections out of the package are realized by ceramics with metallic feed throughs. They are assembled onto the modules (prior to the metallic encapsulation) using sinter-lamination-technology, i.e. the simultaneous build-up lamination and a sintering process. Two application demonstrators were realized in order to show the general viability of the encapsulation process. All used materials are commercially available. Industrial process equipment was used throughout the manufacturing. Subsequent reliability tests provide evidence for the general robustness and functionality of the modules under harsh environmental conditions. This work was part of the Fraunhofer lighthouse project “eHarsh” which was funded by the Fraunhofer Society.
  • Publication
    Design Tool for Temperature Estimation on PCB
    ( 2022)
    Schroeder, Bernd
    ;
    Hoffmann, Stefan
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    Mueller, Olaf
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    Stube, Bernd
    ;
    Hoene, Eckart
    The paper presents a novel thermal analysis approach based on an estimation of current density, power dissipation and temperature distribution of a printed circuit board. The implemented algorithms are integrated in a design tool that can be used as an add-on tool via interfaces to commercial EDA tools. The calculations are based on imported layout data from the EDA tools and not on Gerber data. The current density is calculated with a separate PEEC solver. The developed design tool automatically generates the necessary 3D model, activates the PEEC solver and extracts its calculation results. Subsequently, the implemented thermal solver of the design tool calculates the power dissipation and temperature distribution for a previously assigned current. This efficiently supports the PCB designer already during the layout process. The method is validated by simulations and measurements on typical boards.
  • Publication
    A Novel Quantitative Adhesion Measurement Method for Thin Polymer and Metal Layers for Microelectronic Applications
    ( 2022)
    Woehrmann, Markus
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    Mackowiak, Piotr
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    Schiffer, Michael
    ;
    Lang, K.-D.
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    Schneider-Ramelow, M.
    Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface's fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.
  • Publication
    Experimental and simulative study of warpage behavior for fan-out wafer-level packaging
    ( 2022)
    Dijk, Marius van
    ;
    Huber, Saskia
    ;
    Stegmaier, Andreas
    ;
    Walter, Hans
    ;
    Wittler, Olaf
    ;
    Schneider-Ramelow, M.
    Controlling warpage effects in fan-outwafer-level packaging (FO-WLP) is of key importance for realizing reliable and cost-efficient system in packages (SiPs). However, warpage effects can occur during the manufacturing process, caused by a combination of different processing temperatures, different materials, and the changing properties of the materials (e.g. polymerization and related cure shrinkage). One approach to controlling warpage could be realized by assessing a numerical simulation workflow of the FO-WLP process chain, in which the relevant material properties and geometry are used as input. Since there are many different steps included in the FO-WLP process, accompanied by complex material behavior, this workflow is not straight-forward. In the present paper, the first FO-WLP processing steps are investigated in detail by performing extensive thermo-mechanical material characterization, temperature-dependent warpage measurements, and numerical simulations. The investigation focuses on two epoxy mold compound (EMC) materials with completely different physical properties. The warpage measurements of bi-material (EMC and silicon) samples reveal an irreversible effect after passing certain processing temperatures, which are significant for final warpage at room temperature. A new approach to measuring the coefficient of thermal expansion (CTE) is discussed, using a temperature profile based on the temperature in the process, instead of the three identical temperature ramps suggested by the typical standards. This new approach makes it possible to determine possible shrinkage effects. Within the simulation model, the hysteresis effect observed in the experiment is taken into account by adding a shrinkage strain as well as changing the CTE values during the process. A very good agreement between the experiment and simulation is achieved, which is shown for several demonstrators with different epoxy mold compound materials and thicknesses.
  • Publication
    Panel Level Packaging - Where are the Technology Limits?
    ( 2022)
    Braun, Tanja
    ;
    Hölck, Ole
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    Obst, Mattis
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    Voges, Steve
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    Kahle, Ruben
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    Böttcher, Lars
    ;
    Billaud, Mathilde
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    Stobbe, Lutz
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    Becker, Karl-Friedrich
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    Aschenbrenner, Rolf
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    Voitel, M.
    ;
    Schein, F.-L.
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    Gerholt, L.
    ;
    Schneider-Ramelow, M.
    Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face- down have reached maturity and are introduced in high volume manufacturing. For Fan-out Wafer Level Packaging (FOWLP) clear application trends and technology roadmaps do exist. These range from low density core technology for e.g. RF or PMIC (power management IC) packaging over high density application processor packaging to ultra-high-density applications for networking servers etc.. For panel level packaging it is still not fully clear if the same performance can be achieved as on wafer level as larger process / panel sizes may have higher challenges in process control, accuracy and consistency, material and equipment or handling.Main driver for moving to panel level packaging is of course lowering the packaging cost. More packages can be processed in parallel and panel formats have a much better area utilization (ratio between panel/wafer size and package size) than round wafer shapes. Also, environmentally PLP is advantageous by e.g. lower waste and smaller carbon footprint. However, for both aspects processes with sufficiently high yield are required. This is especially true for FOWLP/PLP RDL last processes as a failure in the RDL will also lead to a loss of packaged die(s).This paper describes current technology developments to access the limits of the panel level packaging technology. Warpage, die shift and fine line capabilities are the main topics here. To better understand the compression molding process as the technological basis of the reconfigured panel and its influence on warpage and die shift a dedicated sensor mold tool has been developed. By integration of temperature, pressure, dielectric and fiber Bragg grating sensors the flowing and curing behavior of epoxy molding compound can be studied in-situ. Results will support process simulations for warpage prediction and more accurate die shift compensation.For large panel processing an adaptive patterning approach might be needed anyhow to achieve a high yield. Here the combination of an intelligent assembly strategy for high speed and sufficient accuracy, capabilities to measure each die position and a maskless lithography process adapting the redistribution layer (RDL) to each die position may lead to a cost-effective high yield process.In addition, a clear trend towards finer lines and spaces as well as smaller via diameters is also demanded for large panel RDL processes. Process developments towards 2 μm lines and spaces and via shrinking on 610x457 mm2 (24'x18') panels are shown including material and process options.In summary this paper will show current PLP technology developments for future high-end applications and will cover at the same time economic and environmental aspects.
  • Publication
    Low-Temperature Processible Highly Conducting Pastes for Printed Electronics Applications
    ( 2022)
    Scenev, V.
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    Szalapak, J.
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    Werft, Lukas
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    Hoelck, Ole
    ;
    Jakubowska, M.
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    Krshiwoblozki, Malte von
    ;
    Kallmayer, Christine
    ;
    Schneider-Ramelow, M.
    Scalable additive manufacturing of printed electronics is a growing field accompanied by increasing demands for reliable and integrable functional flexible printed electronic devices. Herein, a novel type of electrically conducting silver-based pastes for additive manufacturing is demonstrated. These pastes are designed for stencil- and screen-printing and can be post-processed at very low temperatures, at ambient. Furthermore, printed lines made with the pastes exhibit an electrical sheet resistance below 60 mΩ sq-1 even after room temperature and only 25 mΩ sq-1 after two minutes of curing at 90 °C.
  • Publication
    Numerical simulation of transient thermomechanical ageing effects
    ( 2022)
    Dijk, Marius van
    ;
    Huber, Saskia
    ;
    Walter, Hans
    ;
    Wittler, Olaf
    ;
    Schneider-Ramelow, Martin
    Automotive radar and 5G communication systems require for their high frequency functionality substrates with low dielectric constants, which are capable to operate at elevated temperatures for long lifetimes. Special substrates based on laminate Printed Circuit Board (PCB) technology come here into focus due to their cost benefit against ceramic substrates. But the matrix of these substrates is based on polymers like for example PPE (Polyphenylether) or PTFE (Polytetra-floureten). In general, polymers are susceptible to ageing, which may already be initiated at mild conditions and short times (e.g. during the expected usetime) and can have a potential large influence on the reliability as the properties can change massively.To enable the development of reliable electrical components, the behavior during the desired lifetime of the used materials is of importance. In this paper we focus on thermo-oxidative ageing effects of a Radio Frequency (RF) application suitable PCB material and how this effect can be considered transiently in a numerical simulation approach. For this approach, first extensive material characterization was performed on samples aged for different periods of time at 175°C. This temperature was selected as this is the specified maximum operating temperature for the material. These different states of the material were then used within the simulation model, where the ageing process is simulated and a gradual-continuous change of one state to the other is calculated.
  • Publication
    Finite Element Influence Analysis of Power Module Design Options
    ( 2022)
    Dijk, Marius van
    ;
    Wittler, Olaf
    ;
    Hung, P.-C.
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    Lai, W.-H.
    ;
    Hsieh, C.-Y.
    ;
    Wang, T.
    ;
    Schneider-Ramelow, M.
    The electrification trend for the automotive industry (electric- and hybrid electric vehicles EV/HEV) desires the development of application specific power modules with shorter time-to-market for which the reliability is guaranteed over a large time span. Besides the electrical layout of such power modules, numerous variations of the design can be made which include material selection, the used assembly and interconnection technologies and geometrical variations like layer thicknesses and position of certain components.Due to the time efficiency, relative low costs and good possibilities for visualizing thermal and thermomechanical behavior in detail, research and development is focusing nowadays more and more on Finite Element Analysis (FEA). The possibilities of assessing finite element analysis for visualizing influences of certain design choices are discussed in this paper, where the development of a new, low-power automotive power module is used as an example. Moreover, simulation analysis focusses on the complete power module, in order to consider cross influences of design choices.First, a discussion on the static thermal behavior is presented followed by the thermomechanical behavior. As the die attach is prone to show early failure/degradation, a numerical simulation Design of Experiment (DoE) is conducted to visualize the influence of - for example - the heat sink material on die attach reliability. For this purpose, 37 simulation models are evaluated, having different configurations. Additional simulations are performed to investigate the reliability of the electrical connection (ribbon- or wire bond).Special attention is given to the reliability of sintered silver die attach technology. This trend-topic in power electronics is gaining much interest in the recent years where many authors have published results of increasing reliability when the classical soldered die attach is replaced with sintered silver. Experimental tests are performed to investigate the influence of the sintered silver Bond Line Thickness (BLT) and to verify the simulation results. The experiments indicate that even after 2500 thermal shock cycles according to the AQG324 no failure or starting degradation for all bond line thicknesses was observed.
  • Publication
    Sub-TeraHertz Modular Array Layout Optimization under Fabrication Constraints
    ( 2022)
    Dehkordi, S.K.
    ;
    Schwanitz, Oliver
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    Marandi, M.K.
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    Kaiser, Michael
    ;
    Le, Thi Huyen
    ;
    Ndip, Ivan
    ;
    Caire, G.
    Millimeter wave (mmWave) and sub-TeraHertz (sub-THz) multi-user multiple-input multiple-output (MUMIMO) communications operating in the frequency spectrum (30-300 GHz) have already been identified as the most promising candidate for the second phase of 5G and Beyond (5GB) wireless systems aiming to achieve broadband data communications at rates higher than 1 Gb/s while operating in very dense urban small-cell environments. Due to the presence of strong isotropic pathloss in mmWave/sub-THz frequencies, high antenna gains realized through large antenna arrays will be required to mitigate these effects. The small wavelengths under which mmWave and s-THz systems operate, allow for integration of more compact antenna elements. However, the fabrication of such antennas poses challenges such as positioning tolerance. In this work, we introduce a novel modular array synthesis approach and further investigate the effect of non-ideal element/module positions within an array and provide an optimization framework to minimize the expected synthesized array pattern error taking positioning tolerances into account. Furthermore, we use the realized element pattern of the proposed D-Band patch element with an RF bandwidth of over 10 GHz to demonstrate the results of the proposed optimization algorithm.
  • Publication
    Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE
    ( 2022)
    Mackowiak, Piotr
    ;
    Erbacher, Kolja
    ;
    Schiffer, Michael
    ;
    Manier, Charles-Alix
    ;
    Töpper, Michael
    ;
    Ngo, H.-D.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    This article presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched micro electromechanical system (MEMS) SiC Device. By optimizing the process, etch depth of 200 μm with an etch rate of up to 2 μm /min can be achieved for via etching. In addition, a design of experiments (DoEs) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the SiC. Hereby, vertical sidewalls with low micromasking, low microtrenching and an etch rate of up to 4 μm /min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200- μm -thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50- μm thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments MEMSs and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3-D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.