Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Chip embedding into polymer matrices of printed wiring boards
    ( 2006)
    Loeher, T.
    ;
    Neumann, A.
    ;
    Sommer, J.-P.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    The functional density of electronic systems is unfailingly increasing since four decades and is expected to continue so at least within the predictable future. In electronic packaging technology strategies for densification are, however, not as streamlined as in semiconductor industries. In Europe over the past three years efforts have been made to enable functional integration on the system level by direct embedding of chips into printed wiring boards. In the EU funded projects HIDING DIES and SHIFT industrial and academic partners are combining their expertise to achieve stable technology platforms for highest integration. In the present paper two basic technology approaches and results will be presented. In the Chip in Polymer (CIP) technology silicon chips with a thickness between 50 and 80 µm are attached onto a structured core layer of a rigid printed wiring board with very high precision. The core is the laminated with resin coated copper foil on both sides, thereby embedding the chip into the build up layer. Subsequently laser vias are drilled and metallized to the chip bond pads. In the last step the outer copper sheets are structured and interconnected by either mechanical through holes or laser vias. The second approach, Flip Chip in Flex, aims at even thinner system build ups. Here an ultra thin flip chip (20 µm) is mounted onto a structured flexible printed wiring board (thickness 25 µm) and embedded into the build up layer by lamination. Contacts to different layers in the multilayered board are provided by through holes. The pros and contras of each technology will be discussed. In all of these technologies thin silicon chips are embedded into rigid or flexible printed wiring boards and connected either by laser vias or solder contacts. Process technologies, thermo-mechanical simulations of embedded chips, reliability results will be presented and discussed.
  • Publication
    Embedding of active and passive components into printed wiring boards
    ( 2006)
    Löher, T.
    ;
    Neumann, A.
    ;
    Vieroth, R.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    Developments of advanced electronic products and the exploitation of new application fields for microelectronic systems are increasingly accompanied by challenging physical requirements on the system. Examples are light weight for any kind of mobile system, as high as possible degree of miniaturization and robustness against chemicals and body liquids for medical implant systems, possible conformity with bend surfaces for applications in aerospace and automotive. Generally the trend towards further increase of function and component density in future electronic systems is from being saturated. On the other hand there is a considerable pressure to keep lower electronic systems prices. Embedding of active and passive components into build up layers of printed wiring boards has on the long term the potential to comply with both requirements at the same time. The European Union is funding two multinational technology development projects focussing on the embedding of chips and passive components into multilayer printed wiring boards. As examples for embedding of passive components electro less Ni(P) resistors and lamination and structuring of capacitors will be presented. For the passive components deposition control, sheet handling, trimming, lamination into build up layers and post lamination trimming options will be discussed. A technology for the embedding of active chips will be presented. The active chip is therefore thinned down to a thickness of 20 - 30 µm. The chip is then flip chip bonded onto the board wiring using ultra thin solder contacts and subsequently embedded into the laminate layer. The process flow, resulting interconnections and reliability of the systems under different loading conditions will be presented.
  • Publication
    Die hoch-integrierte Leiterplatte mit eingebetteten Chips - Ergebnisse aus dem EU-Projekt Hiding Dies
    ( 2006)
    Neumann, A.
    Das von der Europäischen Union geförderte Projekt HIDING DIES entwickelt eine Technik zur Einbettung aktiver Komponenten, Halbleiterchips mit einer Dicke von 30-60µm, in HDI-Lagen der Leiterplatte. Der Prozess zur Einbettung wird mit den Projektpartnern (AT&S, Datacon, CWM, IMEC, Philips, Nokia, TU Berlin) hinsichtlich der industriellen Umsetzbarkeit entwickelt. Dabei kommt es auf industrienahe Entwicklung an, um eine gute Akzeptanz und möglichst schnelle Einführung der neuen Technologie in die bestehenden Produktionsabläufe zu ermöglichen. Im Rahmen des Projektes wurde ein Prozess entwickelt und parallel dazu thermomechanische Simulationen durchgeführt, die mit den ersten Ergebnissen der Zuverlässigkeit (Reflowtests, Temperaturwechseltest, Feuchtelagerung) präsentiert werden. Die Ergebnisse der Simulation und der Zuverlässigkeitstests zeigen gute Ergebnisse, die eine Motivation für die Weiterentwicklung sind. Der Prozess der Chipeinbettung in HDI-Lagen der Leiterplatte basiert auf derzeit vorhandenen Leiterplattentechnologien. Der Aufbau einer solchen Leiterplatte stellt allerdings neue Anforderungen an die Prozesslogistik und das Design der Leiterplatte. Speziell die neuen Möglichkeiten im Design lassen viel Spielraum für neue Konzepte. So können Komponenten extrem dicht nebeneinander oder übereinander gepackt werden, was für Hochfrequenzschaltungen, extrem dünne Aufbauten/Packages und hochintegrierte Baugruppen interessant ist.